773166a200
available today. This card is a low power 802.11bgn that only does 11n rates up to MCS 7 (that's 65 Mbps in 20Mhz mode and 135 in 40Mhz mode). 802.11n is not yet supported, but will be in the future. The driver still has a problem regarding to the setting of txpower on the card, so don't expect good performance yet. After fixing this problem, an MFC is possible. Special thanks to iXsystems and S Smirnov <tonve at yandex.ru> for help with the purchase of a netbook with this card. Sponsored by: iXsystems, Inc.
232 lines
6.7 KiB
C
232 lines
6.7 KiB
C
/*
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* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_devid.h"
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#include "ar5416/ar5416.h"
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#include "ar5416/ar5416reg.h"
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#include "ar5416/ar5416phy.h"
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#define AR_GPIO_BIT(_gpio) (1 << _gpio)
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/*
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* Configure GPIO Output Mux control
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*/
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static void
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cfgOutputMux(struct ath_hal *ah, uint32_t gpio, uint32_t type)
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{
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int addr;
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uint32_t gpio_shift, reg;
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/* each MUX controls 6 GPIO pins */
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if (gpio > 11)
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addr = AR_GPIO_OUTPUT_MUX3;
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else if (gpio > 5)
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addr = AR_GPIO_OUTPUT_MUX2;
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else
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addr = AR_GPIO_OUTPUT_MUX1;
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/*
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* 5 bits per GPIO pin. Bits 0..4 for 1st pin in that mux,
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* bits 5..9 for 2nd pin, etc.
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*/
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gpio_shift = (gpio % 6) * 5;
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/*
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* From Owl to Merlin 1.0, the value read from MUX1 bit 4 to bit
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* 9 are wrong. Here is hardware's coding:
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* PRDATA[4:0] <= gpio_output_mux[0];
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* PRDATA[9:4] <= gpio_output_mux[1];
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* <==== Bit 4 is used by both gpio_output_mux[0] [1].
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* Currently the max value for gpio_output_mux[] is 6. So bit 4
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* will never be used. So it should be fine that bit 4 won't be
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* able to recover.
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*/
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reg = OS_REG_READ(ah, addr);
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if (addr == AR_GPIO_OUTPUT_MUX1 && !AR_SREV_MERLIN_20_OR_LATER(ah))
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reg = ((reg & 0x1F0) << 1) | (reg & ~0x1F0);
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reg &= ~(0x1f << gpio_shift);
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reg |= type << gpio_shift;
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OS_REG_WRITE(ah, addr, reg);
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}
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/*
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* Configure GPIO Output lines
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*/
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HAL_BOOL
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ar5416GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
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{
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uint32_t gpio_shift, reg;
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HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
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/* NB: type maps directly to hardware */
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cfgOutputMux(ah, gpio, type);
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gpio_shift = gpio << 1; /* 2 bits per output mode */
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reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);
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reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift);
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reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift;
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OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg);
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return AH_TRUE;
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}
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/*
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* Configure GPIO Input lines
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*/
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HAL_BOOL
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ar5416GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
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{
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uint32_t gpio_shift, reg;
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HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
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/* TODO: configure input mux for AR5416 */
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/* If configured as input, set output to tristate */
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gpio_shift = gpio << 1;
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reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);
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reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift);
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reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift;
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OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg);
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return AH_TRUE;
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}
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/*
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* Once configured for I/O - set output lines
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*/
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HAL_BOOL
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ar5416GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
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{
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uint32_t reg;
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HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
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reg = OS_REG_READ(ah, AR_GPIO_IN_OUT);
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if (val & 1)
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reg |= AR_GPIO_BIT(gpio);
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else
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reg &= ~AR_GPIO_BIT(gpio);
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OS_REG_WRITE(ah, AR_GPIO_IN_OUT, reg);
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return AH_TRUE;
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}
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/*
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* Once configured for I/O - get input lines
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*/
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uint32_t
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ar5416GpioGet(struct ath_hal *ah, uint32_t gpio)
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{
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uint32_t bits;
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if (gpio >= AH_PRIVATE(ah)->ah_caps.halNumGpioPins)
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return 0xffffffff;
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/*
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* Read output value for all gpio's, shift it,
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* and verify whether the specific bit is set.
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*/
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if (AR_SREV_KITE_10_OR_LATER(ah))
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bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9285_GPIO_IN_VAL);
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else if (AR_SREV_MERLIN_10_OR_LATER(ah))
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bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR928X_GPIO_IN_VAL);
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else
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bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL);
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return ((bits & AR_GPIO_BIT(gpio)) != 0);
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}
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/*
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* Set the GPIO Interrupt Sync and Async interrupts are both set/cleared.
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* Async GPIO interrupts may not be raised when the chip is put to sleep.
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*/
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void
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ar5416GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
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{
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uint32_t val, mask;
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HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
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if (ilevel == HAL_GPIO_INTR_DISABLE) {
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val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE),
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AR_INTR_ASYNC_ENABLE_GPIO) &~ AR_GPIO_BIT(gpio);
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OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE,
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AR_INTR_ASYNC_ENABLE_GPIO, val);
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mask = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK),
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AR_INTR_ASYNC_MASK_GPIO) &~ AR_GPIO_BIT(gpio);
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OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK,
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AR_INTR_ASYNC_MASK_GPIO, mask);
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/* Clear synchronous GPIO interrupt registers and pending interrupt flag */
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val = MS(OS_REG_READ(ah, AR_INTR_SYNC_ENABLE),
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AR_INTR_SYNC_ENABLE_GPIO) &~ AR_GPIO_BIT(gpio);
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OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE,
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AR_INTR_SYNC_ENABLE_GPIO, val);
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mask = MS(OS_REG_READ(ah, AR_INTR_SYNC_MASK),
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AR_INTR_SYNC_MASK_GPIO) &~ AR_GPIO_BIT(gpio);
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OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK,
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AR_INTR_SYNC_MASK_GPIO, mask);
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val = MS(OS_REG_READ(ah, AR_INTR_SYNC_CAUSE),
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AR_INTR_SYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio);
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OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_CAUSE,
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AR_INTR_SYNC_ENABLE_GPIO, val);
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} else {
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val = MS(OS_REG_READ(ah, AR_GPIO_INTR_POL),
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AR_GPIO_INTR_POL_VAL);
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if (ilevel == HAL_GPIO_INTR_HIGH) {
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/* 0 == interrupt on pin high */
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val &= ~AR_GPIO_BIT(gpio);
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} else if (ilevel == HAL_GPIO_INTR_LOW) {
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/* 1 == interrupt on pin low */
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val |= AR_GPIO_BIT(gpio);
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}
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OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_POL,
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AR_GPIO_INTR_POL_VAL, val);
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/* Change the interrupt mask. */
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val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE),
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AR_INTR_ASYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio);
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OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE,
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AR_INTR_ASYNC_ENABLE_GPIO, val);
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mask = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK),
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AR_INTR_ASYNC_MASK_GPIO) | AR_GPIO_BIT(gpio);
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OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK,
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AR_INTR_ASYNC_MASK_GPIO, mask);
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/* Set synchronous GPIO interrupt registers as well */
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val = MS(OS_REG_READ(ah, AR_INTR_SYNC_ENABLE),
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AR_INTR_SYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio);
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OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE,
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AR_INTR_SYNC_ENABLE_GPIO, val);
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mask = MS(OS_REG_READ(ah, AR_INTR_SYNC_MASK),
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AR_INTR_SYNC_MASK_GPIO) | AR_GPIO_BIT(gpio);
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OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK,
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AR_INTR_SYNC_MASK_GPIO, mask);
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}
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AH5416(ah)->ah_gpioMask = mask; /* for ar5416SetInterrupts */
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}
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