f7a5c9d346
This is a MIPS4KC CPU with various embedded peripherals, including wireless and ethernet support. This commit includes the platform, UART, ethernet MAC and GPIO support. The interrupt-driven GPIO code is disabled for now pending GPIO changes from the submitter. Submitted by: Aleksandr Rybalko <ray@dlink.ua>
127 lines
4.1 KiB
C
127 lines
4.1 KiB
C
/*-
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* Copyright (c) 2010 Aleksandr Rybalko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. The names of the authors may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _RT305XUART_H
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#define _RT305XUART_H
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#undef uart_getreg
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#undef uart_setreg
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#define uart_getreg(bas, reg) \
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bus_space_read_4((bas)->bst, (bas)->bsh, reg)
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#define uart_setreg(bas, reg, value) \
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bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
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/* UART registers */
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#define UART_RX_REG 0x00
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#define UART_TX_REG 0x04
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#define UART_IER_REG 0x08
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#define UART_IER_EDSSI (1<<3) /* Only full UART */
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#define UART_IER_ELSI (1<<2)
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#define UART_IER_ETBEI (1<<1)
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#define UART_IER_ERBFI (1<<0)
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#define UART_IIR_REG 0x0c
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#define UART_IIR_RXFIFO (1<<7)
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#define UART_IIR_TXFIFO (1<<6)
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#define UART_IIR_ID_MST 0
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#define UART_IIR_ID_THRE 1
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#define UART_IIR_ID_DR 2
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#define UART_IIR_ID_LINESTATUS 3
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#define UART_IIR_ID_DR2 6
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#define UART_IIR_ID_SHIFT 1
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#define UART_IIR_ID_MASK 0x0000000e
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#define UART_IIR_INTP (1<<0)
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#define UART_FCR_REG 0x10
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#define UART_FCR_RXTGR_1 (0<<6)
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#define UART_FCR_RXTGR_4 (1<<6)
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#define UART_FCR_RXTGR_8 (2<<6)
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#define UART_FCR_RXTGR_12 (3<<6)
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#define UART_FCR_TXTGR_1 (0<<4)
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#define UART_FCR_TXTGR_4 (1<<4)
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#define UART_FCR_TXTGR_8 (2<<4)
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#define UART_FCR_TXTGR_12 (3<<4)
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#define UART_FCR_DMA (1<<3)
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#define UART_FCR_TXRST (1<<2)
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#define UART_FCR_RXRST (1<<1)
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#define UART_FCR_FIFOEN (1<<0)
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#define UART_LCR_REG 0x14
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#define UART_LCR_DLAB (1<<7)
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#define UART_LCR_BRK (1<<6)
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#define UART_LCR_FPAR (1<<5)
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#define UART_LCR_EVEN (1<<4)
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#define UART_LCR_PEN (1<<3)
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#define UART_LCR_STB_15 (1<<2)
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#define UART_LCR_5B 0
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#define UART_LCR_6B 1
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#define UART_LCR_7B 2
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#define UART_LCR_8B 3
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#define UART_MCR_REG 0x18
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#define UART_MCR_LOOP (1<<4)
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#define UART_MCR_OUT2_L (1<<3) /* Only full UART */
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#define UART_MCR_OUT1_L (1<<2) /* Only full UART */
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#define UART_MCR_RTS_L (1<<1) /* Only full UART */
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#define UART_MCR_DTR_L (1<<0) /* Only full UART */
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#define UART_LSR_REG 0x1c
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#define UART_LSR_ERINF (1<<7)
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#define UART_LSR_TEMT (1<<6)
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#define UART_LSR_THRE (1<<5)
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#define UART_LSR_BI (1<<4)
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#define UART_LSR_FE (1<<3)
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#define UART_LSR_PE (1<<2)
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#define UART_LSR_OE (1<<1)
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#define UART_LSR_DR (1<<0)
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#define UART_MSR_REG 0x20 /* Only full UART */
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#define UART_MSR_DCD (1<<7) /* Only full UART */
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#define UART_MSR_RI (1<<6) /* Only full UART */
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#define UART_MSR_DSR (1<<5) /* Only full UART */
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#define UART_MSR_CTS (1<<4) /* Only full UART */
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#define UART_MSR_DDCD (1<<3) /* Only full UART */
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#define UART_MSR_TERI (1<<2) /* Only full UART */
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#define UART_MSR_DDSR (1<<1) /* Only full UART */
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#define UART_MSR_DCTS (1<<0) /* Only full UART */
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#define UART_CDDL_REG 0x28
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#define UART_CDDLL_REG 0x2c
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#define UART_CDDLH_REG 0x30
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#define UART_IFCTL_REG 0x34
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#define UART_IFCTL_IFCTL (1<<0)
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int uart_cnattach(void);
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#endif /* _RT305XUART_H */
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