03d8fd318a
imcsmb(4) provides smbus(4) support for the SMBus controller functionality in the integrated Memory Controllers (iMCs) embedded in Intel Sandybridge- Xeon, Ivybridge-Xeon, Haswell-Xeon, and Broadwell-Xeon CPUs. Each CPU implements one or more iMCs, depending on the number of cores; each iMC implements two SMBus controllers (iMC-SMBs). *** IMPORTANT NOTE *** Because motherboard firmware or the BMC might try to use the iMC-SMBs for monitoring DIMM temperatures and/or managing an NVDIMM, the driver might need to temporarily disable those functions, or take a hardware interlock, before using the iMC-SMBs. Details on how to do this may vary from board to board, and the procedure may be proprietary. It is strongly suggested that anyone wishing to use this driver contact their motherboard vendor, and modify the driver as described in the manual page and in the driver itself. (For what it's worth, the driver as-is has been tested on various SuperMicro motherboards.) Reviewed by: avg, jhb MFC after: 1 week Relnotes: yes Sponsored by: Panasas Differential Revision: https://reviews.freebsd.org/D14447 Discussed with: avg, ian, jhb Tested by: allanjude (previous version), Panasas
108 lines
3.7 KiB
C
108 lines
3.7 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org)
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*
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* Copyright (c) 2017-2018 Panasas
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV__IMCSMB__IMCSMB_VAR_H_
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#define _DEV__IMCSMB__IMCSMB_VAR_H_
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/endian.h>
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#include <sys/errno.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/syslog.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/atomic.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/smbus/smbconf.h>
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#include "smbus_if.h"
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/* A detailed description of this device is present in imcsmb_pci.c */
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/**
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* The softc for a particular instance of the PCI device associated with a pair
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* of iMC-SMB controllers.
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*
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* Ordinarily, locking would be done with a mutex. However, we might have an
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* NVDIMM connected to this SMBus, and we might need to issue the SAVE command
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* to the NVDIMM from a panic context. Mutex operations are not allowed while
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* the scheduler is stopped, so just use a simple semaphore.
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*
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* If, as described in the manpage, additional steps are needed to stop/restart
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* firmware operations before/after using the controller, then additional fields
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* can be added to this softc.
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*/
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struct imcsmb_pci_softc {
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device_t dev;
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volatile int semaphore;
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};
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void imcsmb_pci_release_bus(device_t dev);
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int imcsmb_pci_request_bus(device_t dev);
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/**
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* PCI config registers for each individual SMBus controller within the iMC.
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* Each iMC-SMB has a separate set of registers. There is an array of these
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* structures for the PCI device, and one of them is passed to driver for the
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* actual iMC-SMB as the IVAR.
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*/
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struct imcsmb_reg_set {
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uint16_t smb_stat;
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uint16_t smb_cmd;
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uint16_t smb_cntl;
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};
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/**
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* The softc for the device associated with a particular iMC-SMB controller.
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* There are two such controllers for each of the PCI devices. The PCI driver
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* tells the iMC-SMB driver which set of registers to use via the IVAR. This
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* technique was suggested by John Baldwin (jhb@).
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*/
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struct imcsmb_softc {
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device_t dev;
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device_t imcsmb_pci; /* The SMBus controller's parent iMC */
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device_t smbus; /* The child smbusX interface */
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struct imcsmb_reg_set *regs; /* The registers this controller uses */
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};
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#endif /* _DEV__IMCSMB__IMCSMB_VAR_H_ */
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/* vi: set ts=8 sw=4 sts=8 noet: */
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