403 lines
9.8 KiB
C
403 lines
9.8 KiB
C
/*-
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* Copyright (c) 2015 Adrian Chadd <adrian@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cons.h>
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#include <sys/kdb.h>
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#include <sys/reboot.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#include <net/ethernet.h>
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#include <machine/clock.h>
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#include <machine/cpu.h>
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#include <machine/cpuregs.h>
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#include <machine/hwfunc.h>
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#include <machine/md_var.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#include <mips/atheros/ar71xxreg.h>
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//#include <mips/atheros/ar934xreg.h>
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#include <mips/atheros/qca955xreg.h>
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#include <mips/atheros/ar71xx_cpudef.h>
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#include <mips/atheros/ar71xx_setup.h>
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#include <mips/atheros/ar71xx_chip.h>
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#include <mips/atheros/qca955x_chip.h>
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static void
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qca955x_chip_detect_mem_size(void)
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{
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}
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static void
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qca955x_chip_detect_sys_frequency(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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uint32_t cpu_pll, ddr_pll;
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uint32_t bootstrap;
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bootstrap = ATH_READ_REG(QCA955X_RESET_REG_BOOTSTRAP);
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if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
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ref_rate = 40 * 1000 * 1000;
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else
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ref_rate = 25 * 1000 * 1000;
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pll = ATH_READ_REG(QCA955X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
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nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
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QCA955X_PLL_CPU_CONFIG_NINT_MASK;
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frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
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cpu_pll = nint * ref_rate / ref_div;
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cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
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cpu_pll /= (1 << out_div);
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pll = ATH_READ_REG(QCA955X_PLL_DDR_CONFIG_REG);
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out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
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nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
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QCA955X_PLL_DDR_CONFIG_NINT_MASK;
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frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
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ddr_pll = nint * ref_rate / ref_div;
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ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
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ddr_pll /= (1 << out_div);
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clk_ctrl = ATH_READ_REG(QCA955X_PLL_CLK_CTRL_REG);
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postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
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cpu_rate = ref_rate;
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else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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cpu_rate = ddr_pll / (postdiv + 1);
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else
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cpu_rate = cpu_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
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if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
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ddr_rate = ref_rate;
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else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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ddr_rate = cpu_pll / (postdiv + 1);
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else
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ddr_rate = ddr_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
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if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
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ahb_rate = ref_rate;
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else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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ahb_rate = ddr_pll / (postdiv + 1);
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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u_ar71xx_ddr_freq = ddr_rate;
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u_ar71xx_cpu_freq = cpu_rate;
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u_ar71xx_ahb_freq = ahb_rate;
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u_ar71xx_wdt_freq = ref_rate;
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u_ar71xx_uart_freq = ref_rate;
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u_ar71xx_mdio_freq = ref_rate;
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u_ar71xx_refclk = ref_rate;
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}
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static void
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qca955x_chip_device_stop(uint32_t mask)
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{
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uint32_t reg;
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reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
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ATH_WRITE_REG(QCA955X_RESET_REG_RESET_MODULE, reg | mask);
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}
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static void
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qca955x_chip_device_start(uint32_t mask)
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{
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uint32_t reg;
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reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
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ATH_WRITE_REG(QCA955X_RESET_REG_RESET_MODULE, reg & ~mask);
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}
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static int
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qca955x_chip_device_stopped(uint32_t mask)
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{
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uint32_t reg;
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reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
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return ((reg & mask) == mask);
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}
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static void
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qca955x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
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{
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/* XXX TODO */
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return;
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}
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static void
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qca955x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
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{
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switch (unit) {
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case 0:
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ATH_WRITE_REG(QCA955X_PLL_ETH_XMII_CONTROL_REG, pll);
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break;
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case 1:
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ATH_WRITE_REG(QCA955X_PLL_ETH_SGMII_CONTROL_REG, pll);
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break;
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default:
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printf("%s: invalid PLL set for arge unit: %d\n",
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__func__, unit);
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return;
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}
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}
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static void
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qca955x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
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{
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switch (id) {
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case AR71XX_CPU_DDR_FLUSH_GE0:
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ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_GE0);
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break;
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case AR71XX_CPU_DDR_FLUSH_GE1:
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ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_GE1);
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break;
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case AR71XX_CPU_DDR_FLUSH_USB:
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ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_USB);
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break;
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case AR71XX_CPU_DDR_FLUSH_PCIE:
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ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_PCIE);
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break;
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case AR71XX_CPU_DDR_FLUSH_WMAC:
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ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_WMAC);
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break;
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case AR71XX_CPU_DDR_FLUSH_PCIE_EP:
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ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_SRC1);
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break;
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case AR71XX_CPU_DDR_FLUSH_CHECKSUM:
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ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_SRC2);
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break;
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default:
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printf("%s: invalid flush (%d)\n", __func__, id);
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}
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}
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static uint32_t
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qca955x_chip_get_eth_pll(unsigned int mac, int speed)
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{
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uint32_t pll;
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switch (speed) {
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case 10:
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pll = QCA955X_PLL_VAL_10;
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break;
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case 100:
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pll = QCA955X_PLL_VAL_100;
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break;
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case 1000:
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pll = QCA955X_PLL_VAL_1000;
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break;
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default:
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printf("%s%d: invalid speed %d\n", __func__, mac, speed);
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pll = 0;
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}
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return (pll);
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}
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static void
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qca955x_chip_reset_ethernet_switch(void)
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{
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#if 0
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ar71xx_device_stop(AR934X_RESET_ETH_SWITCH);
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DELAY(100);
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ar71xx_device_start(AR934X_RESET_ETH_SWITCH);
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DELAY(100);
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#endif
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}
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static void
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qca955x_configure_gmac(uint32_t gmac_cfg)
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{
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uint32_t reg;
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reg = ATH_READ_REG(QCA955X_GMAC_REG_ETH_CFG);
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printf("%s: ETH_CFG=0x%08x\n", __func__, reg);
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reg &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
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reg |= gmac_cfg;
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ATH_WRITE_REG(QCA955X_GMAC_REG_ETH_CFG, reg);
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}
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static void
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qca955x_chip_init_usb_peripheral(void)
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{
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}
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static void
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qca955x_chip_set_mii_if(uint32_t unit, uint32_t mii_mode)
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{
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/*
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* XXX !
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*
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* Nothing to see here; although gmac0 can have its
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* MII configuration changed, the register values
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* are slightly different.
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*/
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}
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/*
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* XXX TODO: fetch default MII divider configuration
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*/
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static void
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qca955x_chip_reset_wmac(void)
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{
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/* XXX TODO */
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}
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static void
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qca955x_chip_init_gmac(void)
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{
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long gmac_cfg;
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if (resource_long_value("qca955x_gmac", 0, "gmac_cfg",
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&gmac_cfg) == 0) {
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printf("%s: gmac_cfg=0x%08lx\n",
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__func__,
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(long) gmac_cfg);
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qca955x_configure_gmac((uint32_t) gmac_cfg);
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}
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}
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/*
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* Reset the NAND Flash Controller.
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*
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* + active=1 means "make it active".
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* + active=0 means "make it inactive".
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*/
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static void
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qca955x_chip_reset_nfc(int active)
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{
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#if 0
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if (active) {
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ar71xx_device_start(AR934X_RESET_NANDF);
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DELAY(100);
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ar71xx_device_start(AR934X_RESET_ETH_SWITCH_ANALOG);
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DELAY(250);
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} else {
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ar71xx_device_stop(AR934X_RESET_ETH_SWITCH_ANALOG);
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DELAY(250);
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ar71xx_device_stop(AR934X_RESET_NANDF);
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DELAY(100);
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}
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#endif
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}
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/*
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* Configure the GPIO output mux setup.
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*
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* The QCA955x has an output mux which allowed
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* certain functions to be configured on any pin.
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* Specifically, the switch PHY link LEDs and
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* WMAC external RX LNA switches are not limited to
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* a specific GPIO pin.
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*/
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static void
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qca955x_chip_gpio_output_configure(int gpio, uint8_t func)
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{
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uint32_t reg, s;
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uint32_t t;
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if (gpio > QCA955X_GPIO_COUNT)
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return;
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reg = QCA955X_GPIO_REG_OUT_FUNC0 + rounddown(gpio, 4);
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s = 8 * (gpio % 4);
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/* read-modify-write */
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t = ATH_READ_REG(AR71XX_GPIO_BASE + reg);
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t &= ~(0xff << s);
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t |= func << s;
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ATH_WRITE_REG(AR71XX_GPIO_BASE + reg, t);
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/* flush write */
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ATH_READ_REG(AR71XX_GPIO_BASE + reg);
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}
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struct ar71xx_cpu_def qca955x_chip_def = {
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&qca955x_chip_detect_mem_size,
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&qca955x_chip_detect_sys_frequency,
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&qca955x_chip_device_stop,
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&qca955x_chip_device_start,
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&qca955x_chip_device_stopped,
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&qca955x_chip_set_pll_ge,
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&qca955x_chip_set_mii_speed,
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&qca955x_chip_set_mii_if,
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&qca955x_chip_get_eth_pll,
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&qca955x_chip_ddr_flush,
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&qca955x_chip_init_usb_peripheral,
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&qca955x_chip_reset_ethernet_switch,
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&qca955x_chip_reset_wmac,
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&qca955x_chip_init_gmac,
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&qca955x_chip_reset_nfc,
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&qca955x_chip_gpio_output_configure,
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};
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