1b75a98556
shared and generalized between our current amd64, i386 and pc98. This is just an initial step that should lead to a more complete effort. For the moment, a very simple porting of cpufreq modules, BIOS calls and the whole MD specific ISA bus part is added to the sub-tree but ideally a lot of code might be added and more shared support should grow. Sponsored by: Sandvine Incorporated Reviewed by: emaste, kib, jhb, imp Discussed on: arch MFC: 3 weeks
140 lines
4.5 KiB
C
140 lines
4.5 KiB
C
/*-
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* Copyright (c) 2004 John Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* The ELCR is a register that controls the trigger mode and polarity of
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* EISA and ISA interrupts. In FreeBSD 3.x and 4.x, the ELCR was only
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* consulted for determining the appropriate trigger mode of EISA
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* interrupts when using an APIC. However, it seems that almost all
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* systems that include PCI also include an ELCR that manages the ISA
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* IRQs 0 through 15. Thus, we check for the presence of an ELCR on
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* every machine by checking to see if the values found at bootup are
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* sane. Note that the polarity of ISA and EISA IRQs are linked to the
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* trigger mode. All edge triggered IRQs use active-hi polarity, and
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* all level triggered interrupts use active-lo polarity.
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*
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* The format of the ELCR is simple: it is a 16-bit bitmap where bit 0
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* controls IRQ 0, bit 1 controls IRQ 1, etc. If the bit is zero, the
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* associated IRQ is edge triggered. If the bit is one, the IRQ is
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* level triggered.
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/systm.h>
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#include <machine/intr_machdep.h>
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#define ELCR_PORT 0x4d0
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#define ELCR_MASK(irq) (1 << (irq))
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static int elcr_status;
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int elcr_found;
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/*
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* Check to see if we have what looks like a valid ELCR. We do this by
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* verifying that IRQs 0, 1, 2, and 13 are all edge triggered.
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*/
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int
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elcr_probe(void)
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{
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int i;
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elcr_status = inb(ELCR_PORT) | inb(ELCR_PORT + 1) << 8;
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if ((elcr_status & (ELCR_MASK(0) | ELCR_MASK(1) | ELCR_MASK(2) |
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ELCR_MASK(8) | ELCR_MASK(13))) != 0)
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return (ENXIO);
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if (bootverbose) {
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printf("ELCR Found. ISA IRQs programmed as:\n");
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for (i = 0; i < 16; i++)
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printf(" %2d", i);
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printf("\n");
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for (i = 0; i < 16; i++)
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if (elcr_status & ELCR_MASK(i))
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printf(" L");
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else
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printf(" E");
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printf("\n");
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}
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if (resource_disabled("elcr", 0))
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return (ENXIO);
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elcr_found = 1;
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return (0);
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}
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/*
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* Returns 1 for level trigger, 0 for edge.
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*/
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enum intr_trigger
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elcr_read_trigger(u_int irq)
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{
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KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
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KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
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if (elcr_status & ELCR_MASK(irq))
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return (INTR_TRIGGER_LEVEL);
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else
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return (INTR_TRIGGER_EDGE);
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}
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/*
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* Set the trigger mode for a specified IRQ. Mode of 0 means edge triggered,
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* and a mode of 1 means level triggered.
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*/
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void
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elcr_write_trigger(u_int irq, enum intr_trigger trigger)
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{
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int new_status;
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KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
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KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
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if (trigger == INTR_TRIGGER_LEVEL)
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new_status = elcr_status | ELCR_MASK(irq);
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else
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new_status = elcr_status & ~ELCR_MASK(irq);
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if (new_status == elcr_status)
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return;
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elcr_status = new_status;
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if (irq >= 8)
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outb(ELCR_PORT + 1, elcr_status >> 8);
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else
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outb(ELCR_PORT, elcr_status & 0xff);
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}
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void
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elcr_resume(void)
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{
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KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
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outb(ELCR_PORT, elcr_status & 0xff);
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outb(ELCR_PORT + 1, elcr_status >> 8);
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}
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