97d40d3d4a
us up to version 2.17.50.20070703, at the last GPLv2 commit. Amongst others, this added upstream support for some FreeBSD-specific things that we previously had to manually hack in, such as the OSABI label support, and so on. There are also quite a number of new files, some for cpu's (e.g. SPU) that we may or may not be interested in, but those can be cleaned up later on, if needed.
127 lines
3.6 KiB
C
127 lines
3.6 KiB
C
/* SPU ELF support for BFD.
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Copyright 2006 Free Software Foundation, Inc.
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This file is part of GDB, GAS, and the GNU binutils.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation,
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Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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/* These two enums are from rel_apu/common/spu_asm_format.h */
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/* definition of instruction format */
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typedef enum {
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RRR,
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RI18,
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RI16,
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RI10,
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RI8,
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RI7,
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RR,
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LBT,
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LBTI,
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IDATA,
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UNKNOWN_IFORMAT
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} spu_iformat;
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/* These values describe assembly instruction arguments. They indicate
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* how to encode, range checking and which relocation to use. */
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typedef enum {
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A_T, /* register at pos 0 */
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A_A, /* register at pos 7 */
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A_B, /* register at pos 14 */
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A_C, /* register at pos 21 */
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A_S, /* special purpose register at pos 7 */
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A_H, /* channel register at pos 7 */
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A_P, /* parenthesis, this has to separate regs from immediates */
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A_S3,
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A_S6,
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A_S7N,
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A_S7,
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A_U7A,
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A_U7B,
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A_S10B,
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A_S10,
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A_S11,
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A_S11I,
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A_S14,
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A_S16,
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A_S18,
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A_R18,
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A_U3,
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A_U5,
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A_U6,
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A_U7,
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A_U14,
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A_X16,
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A_U18,
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A_MAX
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} spu_aformat;
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enum spu_insns {
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#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
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TAG,
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#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
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TAG,
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#include "opcode/spu-insns.h"
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#undef APUOP
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#undef APUOPFB
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M_SPU_MAX
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};
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struct spu_opcode
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{
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spu_iformat insn_type;
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unsigned int opcode;
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char *mnemonic;
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int arg[5];
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};
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#define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size))
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#define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1))
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#define DECODE_INSN_RT(insn) (insn & 0x7f)
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#define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f)
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#define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f)
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#define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f)
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#define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14)
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#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14)
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/* For branching, immediate loads, hbr and lqa/stqa. */
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#define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7)
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#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7)
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/* for stop */
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#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0)
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/* For ila */
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#define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7)
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#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7)
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/* For rotate and shift and generate control mask */
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#define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14)
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#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14)
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/* For float <-> int conversion */
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#define DECODE_INSN_I8(insn) SIGNED_EXTRACT(insn,8,14)
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#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14)
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/* For hbr */
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#define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
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#define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
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#define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
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#define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
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