Merge from CheriBSD:
commit d0c7d235c09fc65dbdb278e7016a96f79c6a49cc
Make the Altera JTAG UART device driver slightly more forgiving of
the foibles of a sub-par hrdware interface by increasing the timeout
for spotting JTAG polling from one to two seconds.
commit 19ed45a18832560dab967c179d83b71081c3a220
Update comment.
commit 8edfe803f033cc8e33229f99894c2b7496a44d5f
Add a comment about a device-driver race condition that could cause the BERI
pipeline to wedge awaiting JTAG in the event that both the low-level console
and the tty layer decide to write to the JTAG FIFO just before JTAG is
disconnected. Resolving this race is a bit tricky as it looks like there
isn't a way to 'give the character back' to the tty layer when we discover
the race. The easy fix is to drop the character, which we don't yet do, but
perhaps should as that is a better outcome than wedging the pipeline.
commit 2ea26cf579c9defcf31e413e7c9b0fbc159237fc
Add a comment about an inherent race with hardware in the Altera JTAG
UART's low-level console code.
Submitted by: rwatson
Sponsored by: DARPA, AFRL
68673ca7df