644 lines
16 KiB
C
644 lines
16 KiB
C
/*
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* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2004 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ar5210/ar5210.h"
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#include "ar5210/ar5210reg.h"
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#include "ar5210/ar5210phy.h"
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#include "ah_eeprom_v1.h"
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#define AR_NUM_GPIO 6 /* 6 GPIO bits */
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#define AR_GPIOD_MASK 0x2f /* 6-bit mask */
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void
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ar5210GetMacAddress(struct ath_hal *ah, uint8_t *mac)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
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}
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HAL_BOOL
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ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
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return AH_TRUE;
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}
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void
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ar5210GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
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{
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static const uint8_t ones[IEEE80211_ADDR_LEN] =
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{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
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OS_MEMCPY(mask, ones, IEEE80211_ADDR_LEN);
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}
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HAL_BOOL
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ar5210SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
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{
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return AH_FALSE;
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}
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/*
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* Read 16 bits of data from the specified EEPROM offset.
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*/
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HAL_BOOL
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ar5210EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)
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{
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(void) OS_REG_READ(ah, AR_EP_AIR(off)); /* activate read op */
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if (!ath_hal_wait(ah, AR_EP_STA,
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AR_EP_STA_RDCMPLT | AR_EP_STA_RDERR, AR_EP_STA_RDCMPLT)) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: read failed for entry 0x%x\n",
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__func__, AR_EP_AIR(off));
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return AH_FALSE;
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}
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*data = OS_REG_READ(ah, AR_EP_RDATA) & 0xffff;
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return AH_TRUE;
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}
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#ifdef AH_SUPPORT_WRITE_EEPROM
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/*
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* Write 16 bits of data to the specified EEPROM offset.
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*/
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HAL_BOOL
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ar5210EepromWrite(struct ath_hal *ah, u_int off, uint16_t data)
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{
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return AH_FALSE;
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}
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#endif /* AH_SUPPORT_WRITE_EEPROM */
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/*
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* Attempt to change the cards operating regulatory domain to the given value
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*/
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HAL_BOOL
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ar5210SetRegulatoryDomain(struct ath_hal *ah,
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uint16_t regDomain, HAL_STATUS *status)
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{
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HAL_STATUS ecode;
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if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
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ecode = HAL_EINVAL;
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goto bad;
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}
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/*
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* Check if EEPROM is configured to allow this; must
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* be a proper version and the protection bits must
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* permit re-writing that segment of the EEPROM.
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*/
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if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
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ecode = HAL_EEWRITE;
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goto bad;
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}
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ecode = HAL_EIO; /* disallow all writes */
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bad:
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if (status)
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*status = ecode;
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return AH_FALSE;
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}
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/*
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* Return the wireless modes (a,b,g,t) supported by hardware.
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*
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* This value is what is actually supported by the hardware
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* and is unaffected by regulatory/country code settings.
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*
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*/
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u_int
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ar5210GetWirelessModes(struct ath_hal *ah)
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{
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/* XXX could enable turbo mode but can't do all rates */
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return HAL_MODE_11A;
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}
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/*
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* Called if RfKill is supported (according to EEPROM). Set the interrupt and
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* GPIO values so the ISR and can disable RF on a switch signal
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*/
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void
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ar5210EnableRfKill(struct ath_hal *ah)
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{
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uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
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int select = MS(rfsilent, AR_EEPROM_RFSILENT_GPIO_SEL);
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int polarity = MS(rfsilent, AR_EEPROM_RFSILENT_POLARITY);
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/*
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* If radio disable switch connection to GPIO bit 0 is enabled
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* program GPIO interrupt.
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* If rfkill bit on eeprom is 1, setupeeprommap routine has already
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* verified that it is a later version of eeprom, it has a place for
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* rfkill bit and it is set to 1, indicating that GPIO bit 0 hardware
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* connection is present.
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*/
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ar5210Gpio0SetIntr(ah, select, (ar5210GpioGet(ah, select) == polarity));
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}
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/*
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* Configure GPIO Output lines
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*/
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HAL_BOOL
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ar5210GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
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{
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HALASSERT(gpio < AR_NUM_GPIO);
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OS_REG_WRITE(ah, AR_GPIOCR,
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(OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))
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| AR_GPIOCR_OUT1(gpio));
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return AH_TRUE;
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}
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/*
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* Configure GPIO Input lines
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*/
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HAL_BOOL
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ar5210GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
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{
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HALASSERT(gpio < AR_NUM_GPIO);
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OS_REG_WRITE(ah, AR_GPIOCR,
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(OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))
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| AR_GPIOCR_IN(gpio));
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return AH_TRUE;
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}
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/*
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* Once configured for I/O - set output lines
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*/
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HAL_BOOL
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ar5210GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
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{
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uint32_t reg;
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HALASSERT(gpio < AR_NUM_GPIO);
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reg = OS_REG_READ(ah, AR_GPIODO);
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reg &= ~(1 << gpio);
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reg |= (val&1) << gpio;
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OS_REG_WRITE(ah, AR_GPIODO, reg);
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return AH_TRUE;
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}
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/*
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* Once configured for I/O - get input lines
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*/
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uint32_t
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ar5210GpioGet(struct ath_hal *ah, uint32_t gpio)
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{
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if (gpio < AR_NUM_GPIO) {
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uint32_t val = OS_REG_READ(ah, AR_GPIODI);
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val = ((val & AR_GPIOD_MASK) >> gpio) & 0x1;
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return val;
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} else {
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return 0xffffffff;
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}
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}
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/*
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* Set the GPIO 0 Interrupt
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*/
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void
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ar5210Gpio0SetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
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{
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uint32_t val = OS_REG_READ(ah, AR_GPIOCR);
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/* Clear the bits that we will modify. */
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val &= ~(AR_GPIOCR_INT_SEL(gpio) | AR_GPIOCR_INT_SELH | AR_GPIOCR_INT_ENA |
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AR_GPIOCR_ALL(gpio));
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val |= AR_GPIOCR_INT_SEL(gpio) | AR_GPIOCR_INT_ENA;
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if (ilevel)
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val |= AR_GPIOCR_INT_SELH;
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/* Don't need to change anything for low level interrupt. */
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OS_REG_WRITE(ah, AR_GPIOCR, val);
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/* Change the interrupt mask. */
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ar5210SetInterrupts(ah, AH5210(ah)->ah_maskReg | HAL_INT_GPIO);
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}
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/*
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* Change the LED blinking pattern to correspond to the connectivity
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*/
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void
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ar5210SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
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{
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uint32_t val;
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val = OS_REG_READ(ah, AR_PCICFG);
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switch (state) {
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case HAL_LED_INIT:
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val &= ~(AR_PCICFG_LED_PEND | AR_PCICFG_LED_ACT);
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break;
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case HAL_LED_RUN:
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/* normal blink when connected */
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val &= ~AR_PCICFG_LED_PEND;
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val |= AR_PCICFG_LED_ACT;
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break;
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default:
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val |= AR_PCICFG_LED_PEND;
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val &= ~AR_PCICFG_LED_ACT;
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break;
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}
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OS_REG_WRITE(ah, AR_PCICFG, val);
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}
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/*
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* Return 1 or 2 for the corresponding antenna that is in use
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*/
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u_int
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ar5210GetDefAntenna(struct ath_hal *ah)
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{
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uint32_t val = OS_REG_READ(ah, AR_STA_ID1);
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return (val & AR_STA_ID1_DEFAULT_ANTENNA ? 2 : 1);
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}
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void
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ar5210SetDefAntenna(struct ath_hal *ah, u_int antenna)
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{
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uint32_t val = OS_REG_READ(ah, AR_STA_ID1);
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if (antenna != (val & AR_STA_ID1_DEFAULT_ANTENNA ? 2 : 1)) {
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/*
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* Antenna change requested, force a toggle of the default.
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*/
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OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_DEFAULT_ANTENNA);
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}
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}
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HAL_ANT_SETTING
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ar5210GetAntennaSwitch(struct ath_hal *ah)
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{
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return HAL_ANT_VARIABLE;
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}
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HAL_BOOL
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ar5210SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
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{
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/* XXX not sure how to fix antenna */
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return (settings == HAL_ANT_VARIABLE);
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}
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/*
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* Change association related fields programmed into the hardware.
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* Writing a valid BSSID to the hardware effectively enables the hardware
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* to synchronize its TSF to the correct beacons and receive frames coming
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* from that BSSID. It is called by the SME JOIN operation.
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*/
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void
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ar5210WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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/* XXX save bssid for possible re-use on reset */
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OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
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OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
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OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
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((assocId & 0x3fff)<<AR_BSS_ID1_AID_S));
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if (assocId == 0)
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OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL);
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else
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OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL);
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}
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/*
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* Get the current hardware tsf for stamlme.
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*/
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uint64_t
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ar5210GetTsf64(struct ath_hal *ah)
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{
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uint32_t low1, low2, u32;
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/* sync multi-word read */
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low1 = OS_REG_READ(ah, AR_TSF_L32);
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u32 = OS_REG_READ(ah, AR_TSF_U32);
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low2 = OS_REG_READ(ah, AR_TSF_L32);
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if (low2 < low1) { /* roll over */
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/*
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* If we are not preempted this will work. If we are
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* then we re-reading AR_TSF_U32 does no good as the
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* low bits will be meaningless. Likewise reading
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* L32, U32, U32, then comparing the last two reads
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* to check for rollover doesn't help if preempted--so
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* we take this approach as it costs one less PCI
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* read which can be noticeable when doing things
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* like timestamping packets in monitor mode.
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*/
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u32++;
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}
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return (((uint64_t) u32) << 32) | ((uint64_t) low2);
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}
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/*
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* Get the current hardware tsf for stamlme.
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*/
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uint32_t
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ar5210GetTsf32(struct ath_hal *ah)
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{
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return OS_REG_READ(ah, AR_TSF_L32);
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}
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/*
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* Reset the current hardware tsf for stamlme
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*/
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void
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ar5210ResetTsf(struct ath_hal *ah)
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{
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uint32_t val = OS_REG_READ(ah, AR_BEACON);
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OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
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}
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/*
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* Grab a semi-random value from hardware registers - may not
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* change often
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*/
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uint32_t
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ar5210GetRandomSeed(struct ath_hal *ah)
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{
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uint32_t nf;
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nf = (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) >> 19) & 0x1ff;
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if (nf & 0x100)
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nf = 0 - ((nf ^ 0x1ff) + 1);
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return (OS_REG_READ(ah, AR_TSF_U32) ^
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OS_REG_READ(ah, AR_TSF_L32) ^ nf);
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}
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/*
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* Detect if our card is present
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*/
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HAL_BOOL
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ar5210DetectCardPresent(struct ath_hal *ah)
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{
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/*
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* Read the Silicon Revision register and compare that
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* to what we read at attach time. If the same, we say
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* a card/device is present.
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*/
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return (AH_PRIVATE(ah)->ah_macRev == (OS_REG_READ(ah, AR_SREV) & 0xff));
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}
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/*
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* Update MIB Counters
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*/
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void
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ar5210UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS *stats)
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{
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stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
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stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
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stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
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stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
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stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
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}
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HAL_BOOL
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ar5210SetSifsTime(struct ath_hal *ah, u_int us)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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if (us > ath_hal_mac_usec(ah, 0x7ff)) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
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__func__, us);
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ahp->ah_sifstime = (u_int) -1; /* restore default handling */
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return AH_FALSE;
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} else {
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/* convert to system clocks */
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OS_REG_RMW_FIELD(ah, AR_IFS0, AR_IFS0_SIFS,
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ath_hal_mac_clks(ah, us));
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ahp->ah_sifstime = us;
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return AH_TRUE;
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}
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}
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u_int
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ar5210GetSifsTime(struct ath_hal *ah)
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{
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u_int clks = OS_REG_READ(ah, AR_IFS0) & 0x7ff;
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return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
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}
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HAL_BOOL
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ar5210SetSlotTime(struct ath_hal *ah, u_int us)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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if (us < HAL_SLOT_TIME_9 || us > ath_hal_mac_usec(ah, 0xffff)) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
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__func__, us);
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ahp->ah_slottime = (u_int) -1; /* restore default handling */
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return AH_FALSE;
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} else {
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/* convert to system clocks */
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OS_REG_WRITE(ah, AR_SLOT_TIME, ath_hal_mac_clks(ah, us));
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ahp->ah_slottime = us;
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return AH_TRUE;
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}
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}
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u_int
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ar5210GetSlotTime(struct ath_hal *ah)
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{
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u_int clks = OS_REG_READ(ah, AR_SLOT_TIME) & 0xffff;
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return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
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}
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HAL_BOOL
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ar5210SetAckTimeout(struct ath_hal *ah, u_int us)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
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__func__, us);
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ahp->ah_acktimeout = (u_int) -1; /* restore default handling */
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return AH_FALSE;
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} else {
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/* convert to system clocks */
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OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
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AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
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ahp->ah_acktimeout = us;
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return AH_TRUE;
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}
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}
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u_int
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ar5210GetAckTimeout(struct ath_hal *ah)
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{
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u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
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return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
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}
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u_int
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ar5210GetAckCTSRate(struct ath_hal *ah)
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{
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return ((AH5210(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5210SetAckCTSRate(struct ath_hal *ah, u_int high)
|
|
{
|
|
struct ath_hal_5210 *ahp = AH5210(ah);
|
|
|
|
if (high) {
|
|
OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
|
|
ahp->ah_staId1Defaults &= ~AR_STA_ID1_ACKCTS_6MB;
|
|
} else {
|
|
OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
|
|
ahp->ah_staId1Defaults |= AR_STA_ID1_ACKCTS_6MB;
|
|
}
|
|
return AH_TRUE;
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5210SetCTSTimeout(struct ath_hal *ah, u_int us)
|
|
{
|
|
struct ath_hal_5210 *ahp = AH5210(ah);
|
|
|
|
if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
|
|
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
|
|
__func__, us);
|
|
ahp->ah_ctstimeout = (u_int) -1; /* restore default handling */
|
|
return AH_FALSE;
|
|
} else {
|
|
/* convert to system clocks */
|
|
OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
|
|
AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
|
|
ahp->ah_ctstimeout = us;
|
|
return AH_TRUE;
|
|
}
|
|
}
|
|
|
|
u_int
|
|
ar5210GetCTSTimeout(struct ath_hal *ah)
|
|
{
|
|
u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
|
|
return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5210SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
|
|
{
|
|
/* nothing to do */
|
|
return AH_TRUE;
|
|
}
|
|
|
|
void
|
|
ar5210SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* Control Adaptive Noise Immunity Parameters
|
|
*/
|
|
HAL_BOOL
|
|
ar5210AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
|
|
{
|
|
return AH_FALSE;
|
|
}
|
|
|
|
void
|
|
ar5210AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats,
|
|
const struct ieee80211_channel *chan)
|
|
{
|
|
}
|
|
|
|
void
|
|
ar5210MibEvent(struct ath_hal *ah, const HAL_NODE_STATS *stats)
|
|
{
|
|
}
|
|
|
|
#define AR_DIAG_SW_DIS_CRYPTO (AR_DIAG_SW_DIS_ENC | AR_DIAG_SW_DIS_DEC)
|
|
|
|
HAL_STATUS
|
|
ar5210GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
|
|
uint32_t capability, uint32_t *result)
|
|
{
|
|
|
|
switch (type) {
|
|
case HAL_CAP_CIPHER: /* cipher handled in hardware */
|
|
return (capability == HAL_CIPHER_WEP ? HAL_OK : HAL_ENOTSUPP);
|
|
default:
|
|
return ath_hal_getcapability(ah, type, capability, result);
|
|
}
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5210SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
|
|
uint32_t capability, uint32_t setting, HAL_STATUS *status)
|
|
{
|
|
|
|
switch (type) {
|
|
case HAL_CAP_DIAG: /* hardware diagnostic support */
|
|
/*
|
|
* NB: could split this up into virtual capabilities,
|
|
* (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
|
|
* seems worth the additional complexity.
|
|
*/
|
|
#ifdef AH_DEBUG
|
|
AH_PRIVATE(ah)->ah_diagreg = setting;
|
|
#else
|
|
AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
|
|
#endif
|
|
OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
|
|
return AH_TRUE;
|
|
case HAL_CAP_RXORN_FATAL: /* HAL_INT_RXORN treated as fatal */
|
|
return AH_FALSE; /* NB: disallow */
|
|
default:
|
|
return ath_hal_setcapability(ah, type, capability,
|
|
setting, status);
|
|
}
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5210GetDiagState(struct ath_hal *ah, int request,
|
|
const void *args, uint32_t argsize,
|
|
void **result, uint32_t *resultsize)
|
|
{
|
|
#ifdef AH_PRIVATE_DIAG
|
|
uint32_t pcicfg;
|
|
HAL_BOOL ok;
|
|
|
|
switch (request) {
|
|
case HAL_DIAG_EEPROM:
|
|
/* XXX */
|
|
break;
|
|
case HAL_DIAG_EEREAD:
|
|
if (argsize != sizeof(uint16_t))
|
|
return AH_FALSE;
|
|
pcicfg = OS_REG_READ(ah, AR_PCICFG);
|
|
OS_REG_WRITE(ah, AR_PCICFG, pcicfg | AR_PCICFG_EEPROMSEL);
|
|
ok = ath_hal_eepromRead(ah, *(const uint16_t *)args, *result);
|
|
OS_REG_WRITE(ah, AR_PCICFG, pcicfg);
|
|
if (ok)
|
|
*resultsize = sizeof(uint16_t);
|
|
return ok;
|
|
}
|
|
#endif
|
|
return ath_hal_getdiagstate(ah, request,
|
|
args, argsize, result, resultsize);
|
|
}
|