5bfac01b59
into a single statement each. Submitted by: Christoph Mallon <christoph dot mallon at gmx dot de> MFC after: 1 week
835 lines
23 KiB
C
835 lines
23 KiB
C
/*-
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* Copyright (c) 2011 Chelsio Communications, Inc.
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* All rights reserved.
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* Written by: Navdeep Parhar <np@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __T4_ADAPTER_H__
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#define __T4_ADAPTER_H__
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/types.h>
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#include <sys/malloc.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <machine/bus.h>
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#include <sys/socket.h>
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#include <sys/sysctl.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <netinet/in.h>
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#include <netinet/tcp_lro.h>
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#include "offload.h"
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#include "firmware/t4fw_interface.h"
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#define T4_CFGNAME "t4fw_cfg"
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#define T4_FWNAME "t4fw"
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MALLOC_DECLARE(M_CXGBE);
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#define CXGBE_UNIMPLEMENTED(s) \
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panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
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#if defined(__i386__) || defined(__amd64__)
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static __inline void
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prefetch(void *x)
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{
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__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
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}
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#else
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#define prefetch(x)
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#endif
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#ifndef SYSCTL_ADD_UQUAD
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#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
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#define sysctl_handle_64 sysctl_handle_quad
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#define CTLTYPE_U64 CTLTYPE_QUAD
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#endif
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#if (__FreeBSD_version >= 900030) || \
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((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
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#define SBUF_DRAIN 1
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#endif
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#ifdef __amd64__
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/* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
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static __inline uint64_t
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t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
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bus_size_t offset)
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{
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KASSERT(tag == X86_BUS_SPACE_MEM,
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("%s: can only handle mem space", __func__));
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return (*(volatile uint64_t *)(handle + offset));
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}
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static __inline void
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t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, uint64_t value)
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{
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KASSERT(tag == X86_BUS_SPACE_MEM,
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("%s: can only handle mem space", __func__));
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*(volatile uint64_t *)(bsh + offset) = value;
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}
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#else
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static __inline uint64_t
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t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
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bus_size_t offset)
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{
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return (uint64_t)bus_space_read_4(tag, handle, offset) +
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((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
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}
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static __inline void
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t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, uint64_t value)
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{
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bus_space_write_4(tag, bsh, offset, value);
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bus_space_write_4(tag, bsh, offset + 4, value >> 32);
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}
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#endif
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struct adapter;
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typedef struct adapter adapter_t;
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enum {
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FW_IQ_QSIZE = 256,
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FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */
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RX_IQ_QSIZE = 1024,
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RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */
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EQ_ESIZE = 64, /* All egress queues use this entry size */
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RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */
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#if MJUMPAGESIZE != MCLBYTES
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FL_BUF_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
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#else
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FL_BUF_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
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#endif
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OFLD_BUF_SIZE = MJUM16BYTES, /* size of fl buffer for TOE rxq */
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CTRL_EQ_QSIZE = 128,
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TX_EQ_QSIZE = 1024,
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TX_SGL_SEGS = 36,
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TX_WR_FLITS = SGE_MAX_WR_LEN / 8
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};
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#ifdef T4_PKT_TIMESTAMP
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#define RX_COPY_THRESHOLD (MINCLSIZE - 8)
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#else
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#define RX_COPY_THRESHOLD MINCLSIZE
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#endif
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enum {
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/* adapter intr_type */
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INTR_INTX = (1 << 0),
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INTR_MSI = (1 << 1),
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INTR_MSIX = (1 << 2)
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};
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enum {
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/* flags understood by begin_synchronized_op */
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HOLD_LOCK = (1 << 0),
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SLEEP_OK = (1 << 1),
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INTR_OK = (1 << 2),
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/* flags understood by end_synchronized_op */
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LOCK_HELD = HOLD_LOCK,
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};
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enum {
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/* adapter flags */
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FULL_INIT_DONE = (1 << 0),
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FW_OK = (1 << 1),
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INTR_DIRECT = (1 << 2), /* direct interrupts for everything */
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MASTER_PF = (1 << 3),
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ADAP_SYSCTL_CTX = (1 << 4),
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TOM_INIT_DONE = (1 << 5),
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CXGBE_BUSY = (1 << 9),
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/* port flags */
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DOOMED = (1 << 0),
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PORT_INIT_DONE = (1 << 1),
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PORT_SYSCTL_CTX = (1 << 2),
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};
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#define IS_DOOMED(pi) ((pi)->flags & DOOMED)
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#define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0)
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#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
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#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
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#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
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struct port_info {
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device_t dev;
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struct adapter *adapter;
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struct ifnet *ifp;
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struct ifmedia media;
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struct mtx pi_lock;
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char lockname[16];
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unsigned long flags;
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int if_flags;
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uint16_t viid;
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int16_t xact_addr_filt;/* index of exact MAC address filter */
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uint16_t rss_size; /* size of VI's RSS table slice */
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uint8_t lport; /* associated offload logical port */
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int8_t mdio_addr;
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uint8_t port_type;
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uint8_t mod_type;
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uint8_t port_id;
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uint8_t tx_chan;
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/* These need to be int as they are used in sysctl */
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int ntxq; /* # of tx queues */
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int first_txq; /* index of first tx queue */
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int nrxq; /* # of rx queues */
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int first_rxq; /* index of first rx queue */
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#ifdef TCP_OFFLOAD
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int nofldtxq; /* # of offload tx queues */
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int first_ofld_txq; /* index of first offload tx queue */
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int nofldrxq; /* # of offload rx queues */
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int first_ofld_rxq; /* index of first offload rx queue */
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#endif
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int tmr_idx;
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int pktc_idx;
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int qsize_rxq;
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int qsize_txq;
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struct link_config link_cfg;
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struct port_stats stats;
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eventhandler_tag vlan_c;
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struct callout tick;
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struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
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uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
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};
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struct fl_sdesc {
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struct mbuf *m;
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bus_dmamap_t map;
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caddr_t cl;
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uint8_t tag_idx; /* the sc->fl_tag this map comes from */
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#ifdef INVARIANTS
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__be64 ba_tag;
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#endif
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};
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struct tx_desc {
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__be64 flit[8];
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};
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struct tx_map {
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struct mbuf *m;
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bus_dmamap_t map;
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};
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/* DMA maps used for tx */
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struct tx_maps {
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struct tx_map *maps;
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uint32_t map_total; /* # of DMA maps */
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uint32_t map_pidx; /* next map to be used */
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uint32_t map_cidx; /* reclaimed up to this index */
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uint32_t map_avail; /* # of available maps */
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};
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struct tx_sdesc {
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uint8_t desc_used; /* # of hardware descriptors used by the WR */
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uint8_t credits; /* NIC txq: # of frames sent out in the WR */
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};
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enum {
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/* iq flags */
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IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
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IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
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IQ_INTR = (1 << 2), /* iq takes direct interrupt */
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IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
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/* iq state */
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IQS_DISABLED = 0,
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IQS_BUSY = 1,
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IQS_IDLE = 2,
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};
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/*
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* Ingress Queue: T4 is producer, driver is consumer.
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*/
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struct sge_iq {
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bus_dma_tag_t desc_tag;
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bus_dmamap_t desc_map;
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bus_addr_t ba; /* bus address of descriptor ring */
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uint32_t flags;
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uint16_t abs_id; /* absolute SGE id for the iq */
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int8_t intr_pktc_idx; /* packet count threshold index */
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int8_t pad0;
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__be64 *desc; /* KVA of descriptor ring */
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volatile int state;
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struct adapter *adapter;
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const __be64 *cdesc; /* current descriptor */
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uint8_t gen; /* generation bit */
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uint8_t intr_params; /* interrupt holdoff parameters */
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uint8_t intr_next; /* XXX: holdoff for next interrupt */
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uint8_t esize; /* size (bytes) of each entry in the queue */
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uint16_t qsize; /* size (# of entries) of the queue */
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uint16_t cidx; /* consumer index */
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uint16_t cntxt_id; /* SGE context id for the iq */
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STAILQ_ENTRY(sge_iq) link;
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};
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enum {
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EQ_CTRL = 1,
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EQ_ETH = 2,
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#ifdef TCP_OFFLOAD
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EQ_OFLD = 3,
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#endif
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/* eq flags */
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EQ_TYPEMASK = 7, /* 3 lsbits hold the type */
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EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */
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EQ_DOOMED = (1 << 4), /* about to be destroyed */
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EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */
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EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */
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};
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/*
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* Egress Queue: driver is producer, T4 is consumer.
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*
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* Note: A free list is an egress queue (driver produces the buffers and T4
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* consumes them) but it's special enough to have its own struct (see sge_fl).
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*/
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struct sge_eq {
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unsigned int flags; /* MUST be first */
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unsigned int cntxt_id; /* SGE context id for the eq */
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bus_dma_tag_t desc_tag;
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bus_dmamap_t desc_map;
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char lockname[16];
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struct mtx eq_lock;
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struct tx_desc *desc; /* KVA of descriptor ring */
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bus_addr_t ba; /* bus address of descriptor ring */
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struct sge_qstat *spg; /* status page, for convenience */
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uint16_t cap; /* max # of desc, for convenience */
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uint16_t avail; /* available descriptors, for convenience */
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uint16_t qsize; /* size (# of entries) of the queue */
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uint16_t cidx; /* consumer idx (desc idx) */
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uint16_t pidx; /* producer idx (desc idx) */
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uint16_t pending; /* # of descriptors used since last doorbell */
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uint16_t iqid; /* iq that gets egr_update for the eq */
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uint8_t tx_chan; /* tx channel used by the eq */
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struct task tx_task;
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struct callout tx_callout;
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/* stats */
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uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */
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uint32_t unstalled; /* recovered from stall */
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};
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enum {
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FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
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FL_DOOMED = (1 << 1), /* about to be destroyed */
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};
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#define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat)
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#define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat)
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struct sge_fl {
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bus_dma_tag_t desc_tag;
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bus_dmamap_t desc_map;
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bus_dma_tag_t tag[FL_BUF_SIZES];
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uint8_t tag_idx;
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struct mtx fl_lock;
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char lockname[16];
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int flags;
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__be64 *desc; /* KVA of descriptor ring, ptr to addresses */
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bus_addr_t ba; /* bus address of descriptor ring */
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struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
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uint32_t cap; /* max # of buffers, for convenience */
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uint16_t qsize; /* size (# of entries) of the queue */
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uint16_t cntxt_id; /* SGE context id for the freelist */
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uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */
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uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */
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uint32_t needed; /* # of buffers needed to fill up fl. */
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uint32_t lowat; /* # of buffers <= this means fl needs help */
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uint32_t pending; /* # of bufs allocated since last doorbell */
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unsigned int dmamap_failed;
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TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
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};
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/* txq: SGE egress queue + what's needed for Ethernet NIC */
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struct sge_txq {
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struct sge_eq eq; /* MUST be first */
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struct ifnet *ifp; /* the interface this txq belongs to */
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bus_dma_tag_t tx_tag; /* tag for transmit buffers */
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struct buf_ring *br; /* tx buffer ring */
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struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
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struct mbuf *m; /* held up due to temporary resource shortage */
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struct tx_maps txmaps;
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/* stats for common events first */
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uint64_t txcsum; /* # of times hardware assisted with checksum */
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uint64_t tso_wrs; /* # of TSO work requests */
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uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
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uint64_t imm_wrs; /* # of work requests with immediate data */
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uint64_t sgl_wrs; /* # of work requests with direct SGL */
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uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
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uint64_t txpkts_wrs; /* # of coalesced tx work requests */
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uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */
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/* stats for not-that-common events */
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uint32_t no_dmamap; /* no DMA map to load the mbuf */
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uint32_t no_desc; /* out of hardware descriptors */
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} __aligned(CACHE_LINE_SIZE);
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/* rxq: SGE ingress queue + SGE free list + miscellaneous items */
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struct sge_rxq {
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struct sge_iq iq; /* MUST be first */
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struct sge_fl fl; /* MUST follow iq */
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struct ifnet *ifp; /* the interface this rxq belongs to */
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#if defined(INET) || defined(INET6)
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struct lro_ctrl lro; /* LRO state */
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#endif
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/* stats for common events first */
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uint64_t rxcsum; /* # of times hardware assisted with checksum */
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uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
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/* stats for not-that-common events */
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} __aligned(CACHE_LINE_SIZE);
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static inline struct sge_rxq *
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iq_to_rxq(struct sge_iq *iq)
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{
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return (__containerof(iq, struct sge_rxq, iq));
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}
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#ifdef TCP_OFFLOAD
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/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
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struct sge_ofld_rxq {
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struct sge_iq iq; /* MUST be first */
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struct sge_fl fl; /* MUST follow iq */
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} __aligned(CACHE_LINE_SIZE);
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static inline struct sge_ofld_rxq *
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iq_to_ofld_rxq(struct sge_iq *iq)
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{
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return (__containerof(iq, struct sge_ofld_rxq, iq));
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}
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#endif
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struct wrqe {
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STAILQ_ENTRY(wrqe) link;
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struct sge_wrq *wrq;
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int wr_len;
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uint64_t wr[] __aligned(16);
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};
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/*
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* wrq: SGE egress queue that is given prebuilt work requests. Both the control
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* and offload tx queues are of this type.
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*/
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struct sge_wrq {
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struct sge_eq eq; /* MUST be first */
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struct adapter *adapter;
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/* List of WRs held up due to lack of tx descriptors */
|
|
STAILQ_HEAD(, wrqe) wr_list;
|
|
|
|
/* stats for common events first */
|
|
|
|
uint64_t tx_wrs; /* # of tx work requests */
|
|
|
|
/* stats for not-that-common events */
|
|
|
|
uint32_t no_desc; /* out of hardware descriptors */
|
|
} __aligned(CACHE_LINE_SIZE);
|
|
|
|
struct sge {
|
|
int timer_val[SGE_NTIMERS];
|
|
int counter_val[SGE_NCOUNTERS];
|
|
int fl_starve_threshold;
|
|
|
|
int nrxq; /* total # of Ethernet rx queues */
|
|
int ntxq; /* total # of Ethernet tx tx queues */
|
|
#ifdef TCP_OFFLOAD
|
|
int nofldrxq; /* total # of TOE rx queues */
|
|
int nofldtxq; /* total # of TOE tx queues */
|
|
#endif
|
|
int niq; /* total # of ingress queues */
|
|
int neq; /* total # of egress queues */
|
|
|
|
struct sge_iq fwq; /* Firmware event queue */
|
|
struct sge_wrq mgmtq; /* Management queue (control queue) */
|
|
struct sge_wrq *ctrlq; /* Control queues */
|
|
struct sge_txq *txq; /* NIC tx queues */
|
|
struct sge_rxq *rxq; /* NIC rx queues */
|
|
#ifdef TCP_OFFLOAD
|
|
struct sge_wrq *ofld_txq; /* TOE tx queues */
|
|
struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
|
|
#endif
|
|
|
|
uint16_t iq_start;
|
|
int eq_start;
|
|
struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
|
|
struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
|
|
};
|
|
|
|
struct rss_header;
|
|
typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
|
|
struct mbuf *);
|
|
typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
|
|
typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
|
|
|
|
struct adapter {
|
|
SLIST_ENTRY(adapter) link;
|
|
device_t dev;
|
|
struct cdev *cdev;
|
|
|
|
/* PCIe register resources */
|
|
int regs_rid;
|
|
struct resource *regs_res;
|
|
int msix_rid;
|
|
struct resource *msix_res;
|
|
bus_space_handle_t bh;
|
|
bus_space_tag_t bt;
|
|
bus_size_t mmio_len;
|
|
|
|
unsigned int pf;
|
|
unsigned int mbox;
|
|
|
|
/* Interrupt information */
|
|
int intr_type;
|
|
int intr_count;
|
|
struct irq {
|
|
struct resource *res;
|
|
int rid;
|
|
void *tag;
|
|
} *irq;
|
|
|
|
bus_dma_tag_t dmat; /* Parent DMA tag */
|
|
|
|
struct sge sge;
|
|
|
|
struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */
|
|
struct port_info *port[MAX_NPORTS];
|
|
uint8_t chan_map[NCHAN];
|
|
uint32_t filter_mode;
|
|
|
|
#ifdef TCP_OFFLOAD
|
|
void *tom_softc; /* (struct tom_data *) */
|
|
struct tom_tunables tt;
|
|
#endif
|
|
struct l2t_data *l2t; /* L2 table */
|
|
struct tid_info tids;
|
|
|
|
int open_device_map;
|
|
#ifdef TCP_OFFLOAD
|
|
int offload_map;
|
|
#endif
|
|
int flags;
|
|
|
|
char fw_version[32];
|
|
unsigned int cfcsum;
|
|
struct adapter_params params;
|
|
struct t4_virt_res vres;
|
|
|
|
uint16_t linkcaps;
|
|
uint16_t niccaps;
|
|
uint16_t toecaps;
|
|
uint16_t rdmacaps;
|
|
uint16_t iscsicaps;
|
|
uint16_t fcoecaps;
|
|
|
|
struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
|
|
|
|
struct mtx sc_lock;
|
|
char lockname[16];
|
|
|
|
/* Starving free lists */
|
|
struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
|
|
TAILQ_HEAD(, sge_fl) sfl;
|
|
struct callout sfl_callout;
|
|
|
|
an_handler_t an_handler __aligned(CACHE_LINE_SIZE);
|
|
fw_msg_handler_t fw_msg_handler[4]; /* NUM_FW6_TYPES */
|
|
cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
|
|
|
|
#ifdef INVARIANTS
|
|
const char *last_op;
|
|
const void *last_op_thr;
|
|
#endif
|
|
};
|
|
|
|
#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
|
|
#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
|
|
#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
|
|
#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
|
|
|
|
/* XXX: not bulletproof, but much better than nothing */
|
|
#define ASSERT_SYNCHRONIZED_OP(sc) \
|
|
KASSERT(IS_BUSY(sc) && \
|
|
(mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
|
|
("%s: operation not synchronized.", __func__))
|
|
|
|
#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
|
|
#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
|
|
#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
|
|
#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
|
|
|
|
#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
|
|
#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
|
|
#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
|
|
#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
|
|
#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
|
|
|
|
#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
|
|
#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
|
|
#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
|
|
#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
|
|
|
|
#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
|
|
#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
|
|
#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
|
|
#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
|
|
#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
|
|
|
|
#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
|
|
#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
|
|
#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
|
|
#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
|
|
#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
|
|
|
|
#define for_each_txq(pi, iter, q) \
|
|
for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \
|
|
iter < pi->ntxq; ++iter, ++q)
|
|
#define for_each_rxq(pi, iter, q) \
|
|
for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \
|
|
iter < pi->nrxq; ++iter, ++q)
|
|
#define for_each_ofld_txq(pi, iter, q) \
|
|
for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \
|
|
iter < pi->nofldtxq; ++iter, ++q)
|
|
#define for_each_ofld_rxq(pi, iter, q) \
|
|
for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \
|
|
iter < pi->nofldrxq; ++iter, ++q)
|
|
|
|
/* One for errors, one for firmware events */
|
|
#define T4_EXTRA_INTR 2
|
|
|
|
static inline uint32_t
|
|
t4_read_reg(struct adapter *sc, uint32_t reg)
|
|
{
|
|
|
|
return bus_space_read_4(sc->bt, sc->bh, reg);
|
|
}
|
|
|
|
static inline void
|
|
t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
|
|
{
|
|
|
|
bus_space_write_4(sc->bt, sc->bh, reg, val);
|
|
}
|
|
|
|
static inline uint64_t
|
|
t4_read_reg64(struct adapter *sc, uint32_t reg)
|
|
{
|
|
|
|
return t4_bus_space_read_8(sc->bt, sc->bh, reg);
|
|
}
|
|
|
|
static inline void
|
|
t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
|
|
{
|
|
|
|
t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
|
|
}
|
|
|
|
static inline void
|
|
t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
|
|
{
|
|
|
|
*val = pci_read_config(sc->dev, reg, 1);
|
|
}
|
|
|
|
static inline void
|
|
t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
|
|
{
|
|
|
|
pci_write_config(sc->dev, reg, val, 1);
|
|
}
|
|
|
|
static inline void
|
|
t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
|
|
{
|
|
|
|
*val = pci_read_config(sc->dev, reg, 2);
|
|
}
|
|
|
|
static inline void
|
|
t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
|
|
{
|
|
|
|
pci_write_config(sc->dev, reg, val, 2);
|
|
}
|
|
|
|
static inline void
|
|
t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
|
|
{
|
|
|
|
*val = pci_read_config(sc->dev, reg, 4);
|
|
}
|
|
|
|
static inline void
|
|
t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
|
|
{
|
|
|
|
pci_write_config(sc->dev, reg, val, 4);
|
|
}
|
|
|
|
static inline struct port_info *
|
|
adap2pinfo(struct adapter *sc, int idx)
|
|
{
|
|
|
|
return (sc->port[idx]);
|
|
}
|
|
|
|
static inline void
|
|
t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
|
|
{
|
|
|
|
bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN);
|
|
}
|
|
|
|
static inline bool is_10G_port(const struct port_info *pi)
|
|
{
|
|
|
|
return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
|
|
}
|
|
|
|
static inline int tx_resume_threshold(struct sge_eq *eq)
|
|
{
|
|
|
|
return (eq->qsize / 4);
|
|
}
|
|
|
|
/* t4_main.c */
|
|
void t4_tx_task(void *, int);
|
|
void t4_tx_callout(void *);
|
|
int t4_os_find_pci_capability(struct adapter *, int);
|
|
int t4_os_pci_save_state(struct adapter *);
|
|
int t4_os_pci_restore_state(struct adapter *);
|
|
void t4_os_portmod_changed(const struct adapter *, int);
|
|
void t4_os_link_changed(struct adapter *, int, int);
|
|
void t4_iterate(void (*)(struct adapter *, void *), void *);
|
|
int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
|
|
int t4_register_an_handler(struct adapter *, an_handler_t);
|
|
int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
|
|
int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
|
|
int begin_synchronized_op(struct adapter *, struct port_info *, int, char *);
|
|
void end_synchronized_op(struct adapter *, int);
|
|
|
|
/* t4_sge.c */
|
|
void t4_sge_modload(void);
|
|
int t4_sge_init(struct adapter *);
|
|
int t4_create_dma_tag(struct adapter *);
|
|
int t4_destroy_dma_tag(struct adapter *);
|
|
int t4_setup_adapter_queues(struct adapter *);
|
|
int t4_teardown_adapter_queues(struct adapter *);
|
|
int t4_setup_port_queues(struct port_info *);
|
|
int t4_teardown_port_queues(struct port_info *);
|
|
int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int);
|
|
void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t);
|
|
void t4_intr_all(void *);
|
|
void t4_intr(void *);
|
|
void t4_intr_err(void *);
|
|
void t4_intr_evt(void *);
|
|
void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
|
|
int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *);
|
|
void t4_update_fl_bufsize(struct ifnet *);
|
|
int can_resume_tx(struct sge_eq *);
|
|
|
|
static inline struct wrqe *
|
|
alloc_wrqe(int wr_len, struct sge_wrq *wrq)
|
|
{
|
|
int len = offsetof(struct wrqe, wr) + wr_len;
|
|
struct wrqe *wr;
|
|
|
|
wr = malloc(len, M_CXGBE, M_NOWAIT);
|
|
if (__predict_false(wr == NULL))
|
|
return (NULL);
|
|
wr->wr_len = wr_len;
|
|
wr->wrq = wrq;
|
|
return (wr);
|
|
}
|
|
|
|
static inline void *
|
|
wrtod(struct wrqe *wr)
|
|
{
|
|
return (&wr->wr[0]);
|
|
}
|
|
|
|
static inline void
|
|
free_wrqe(struct wrqe *wr)
|
|
{
|
|
free(wr, M_CXGBE);
|
|
}
|
|
|
|
static inline void
|
|
t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
|
|
{
|
|
struct sge_wrq *wrq = wr->wrq;
|
|
|
|
TXQ_LOCK(wrq);
|
|
t4_wrq_tx_locked(sc, wrq, wr);
|
|
TXQ_UNLOCK(wrq);
|
|
}
|
|
|
|
#endif
|