mav 1efe697292 Make DMAR allow Intel NTB device to access its own BAR0. ... I have no good explanation why it happens, but I found that in B2B mode at least Xeon v4 NTB leaks accesses to its configuration memory at BAR0 originated from the link side to its host side. DMAR predictably blocks those, making access to remote scratchpad registers in B2B mode impossible. This change creates identity mapping in DMAR covering the BAR0 addresses, making the NTB work fine with DMAR enabled. It seems like allowing single 4KB range at 32KB offset may be enough, but I don't see a reason to be so specific. MFC after: 1 week Sponsored by: iXsystems, Inc.		2019-11-28 02:40:12 +00:00
..
ntb_hw_amd.c	Make ntb(4) send bus_get_dma_tag() requests to parent buses passing real	2019-11-14 04:34:58 +00:00
ntb_hw_amd.h	Add support for PCI Device ID 0x148B in ntb_hw_amd driver.	2019-08-14 22:35:11 +00:00
ntb_hw_intel.c	Make DMAR allow Intel NTB device to access its own BAR0.	2019-11-28 02:40:12 +00:00
ntb_hw_intel.h
ntb_hw_plx.c	Call bus_dma_dmar_set_buswide(9) added in r354830.	2019-11-19 02:03:10 +00:00