mav 0bf5f10c46 MFp4: ... - Remove most of direct relations between ATA(4) peripherial and controller levels. It makes logic more transparent and is a mandatory step to wrap ATA(4) controller level into ATA-native CAM SIM. - Tune AHCI and SATA2 SiI drivers memory allocation a bit to allow bigger I/O transaction sizes without additional cost.		2009-10-31 13:24:14 +00:00
..
arm	In r197963, a race with thread being selected for signal delivery	2009-10-27 10:47:58 +00:00
at91	- Proprely intialize UART parameters at probe stage, so uart(4)	2009-08-15 15:15:20 +00:00
compile
conf	Sync with other GENERIC kernel configs:	2009-10-13 19:04:01 +00:00
include	Define architectural load bases for PIE binaries. Addresses were selected	2009-10-10 15:31:24 +00:00
mv	MFp4:	2009-10-31 13:24:14 +00:00
sa11x0	Map DPCPU pages into ARM kernel VA space.	2009-07-01 20:07:44 +00:00
xscale	Remove remaining bits of performance counter support.	2009-10-03 13:59:15 +00:00