freebsd-skq/sys/amd64/vmm
Scott Long da761f3b1f Implement VT-d capability detection on chipsets that have multiple
translation units with differing capabilities

From the author via Bugzilla:
---
When an attempt is made to passthrough a PCI device to a bhyve VM
(causing initialisation of IOMMU) on certain Intel chipsets using
VT-d the PCI bus stops working entirely. This issue occurs on the
E3-1275 v5 processor on C236 chipset and has also been encountered
by others on the forums with different hardware in the Skylake
series.

The chipset has two VT-d translation units. The issue is caused by
an attempt to use the VT-d device-IOTLB capability that is
supported by only the first unit for devices attached to the
second unit which lacks that capability. Only the capabilities of
the first unit are checked and are assumed to be the same for all
units.

Attached is a patch to rectify this issue by determining which
unit is responsible for the device being added to a domain and
then checking that unit's device-IOTLB capability. In addition to
this a few fixes have been made to other instances where the first
unit's capabilities are assumed for all units for domains they
share. In these cases a mutual set of capabilities is determined.
The patch should hopefully fix any bugs for current/future
hardware with multiple translation units supporting different
capabilities.

A description is on the forums at
https://forums.freebsd.org/threads/pci-passthrough-bhyve-usb-xhci.65235
The thread includes observations by other users of the bug
occurring, and description as well as confirmation of the fix.
I'd also like to thank Ordoban for their help.

---
Personally tested on a Skylake laptop, Skylake Xeon server, and
a Xeon-D-1541, passing through XHCI and NVMe functions.  Passthru
is hit-or-miss to the point of being unusable without this
patch.

PR: 229852
Submitted by: callum@aitchison.org
MFC after: 1 week
2019-06-19 06:41:07 +00:00
..
amd Add accessor function for vm->maxcpus 2019-04-25 22:51:36 +00:00
intel Implement VT-d capability detection on chipsets that have multiple 2019-06-19 06:41:07 +00:00
io Support MSI-X for passthrough devices with a separate PBA BAR. 2019-06-05 19:30:32 +00:00
vmm_dev.c Add accessor function for vm->maxcpus 2019-04-25 22:51:36 +00:00
vmm_host.c Correct undesirable interaction between caching of %cr4 in bhyve and 2018-04-24 13:44:19 +00:00
vmm_host.h sys/amd64: further adoption of SPDX licensing ID tags. 2017-11-27 15:03:07 +00:00
vmm_instruction_emul.c Emulate the "ADD reg, r/m" instruction (opcode 03H). 2019-05-03 21:48:42 +00:00
vmm_ioport.c Add SPDX tags to vmm(4). 2018-06-13 07:02:58 +00:00
vmm_ioport.h Add SPDX tags to vmm(4). 2018-06-13 07:02:58 +00:00
vmm_ktr.h sys/amd64: further adoption of SPDX licensing ID tags. 2017-11-27 15:03:07 +00:00
vmm_lapic.c Add accessor function for vm->maxcpus 2019-04-25 22:51:36 +00:00
vmm_lapic.h sys/amd64: further adoption of SPDX licensing ID tags. 2017-11-27 15:03:07 +00:00
vmm_mem.c sys/amd64: further adoption of SPDX licensing ID tags. 2017-11-27 15:03:07 +00:00
vmm_mem.h sys/amd64: further adoption of SPDX licensing ID tags. 2017-11-27 15:03:07 +00:00
vmm_stat.c Add accessor function for vm->maxcpus 2019-04-25 22:51:36 +00:00
vmm_stat.h sys: further adoption of SPDX licensing ID tags. 2017-11-20 19:43:44 +00:00
vmm_util.c sys/amd64: further adoption of SPDX licensing ID tags. 2017-11-27 15:03:07 +00:00
vmm_util.h sys/amd64: further adoption of SPDX licensing ID tags. 2017-11-27 15:03:07 +00:00
vmm.c Provide separate accounting for user-wired pages. 2019-05-13 16:38:48 +00:00
x86.c Expose the MD_CLEAR capability used by Intel MDS mitigations to guests. 2019-05-18 21:20:38 +00:00
x86.h vmm(4): Take steps towards multicore bhyve AMD support 2019-01-16 02:19:04 +00:00