kib b19d7b3a7d Reduce default shift used to calculate the max frequency for the TSC ... timecounter to 1, and correspondingly increase the precision of the gettimeofday(2) and related functions in the default configuration. The motivation for the TSC-low timecounter, as described in the r222866, seems to provide a workaround for the non-serializing behaviour of the RDTSC on some Intel hardware. Tests demonstrate that even with the pre-shift of 8, the cross-core non-monotonicity of the RDTSC is still observed reliably, e.g. on the Nehalems. The r238755 and r238973 implemented the proper fix for the issue. The pre-shift of 1 is applied to keep TSC not overflowing for the frequency of hardclock down to 2 sec/intr. The pre-shift is made a tunable to allow the easy debugging of the issues users could see with the shift being too low. Reviewed by: bde MFC after: 2 weeks		2013-01-30 12:43:10 +00:00
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acpica	Merge ACPICA 20120816.	2012-08-16 20:54:52 +00:00
bios	Add missing header needed by free(9).	2012-09-30 15:42:20 +00:00
cpufreq	This isn't functionally identical. In some cases a hint to disable	2012-10-22 13:06:09 +00:00
include	Add macros required to enable VMX operation on Intel processors.	2013-01-05 04:20:14 +00:00
isa	This isn't functionally identical. In some cases a hint to disable	2012-10-22 13:06:09 +00:00
pci	Trim stray blank line.	2012-04-11 21:00:33 +00:00
x86	Reduce default shift used to calculate the max frequency for the TSC	2013-01-30 12:43:10 +00:00