39d22b9678
Certain invalid operations trigger hardware error conditions. Error conditions that only halt one channel can be detected and recovered by resetting the channel. Error conditions that halt the whole device are generally not recoverable. Add a sysctl to inject channel-fatal HW errors, 'dev.ioat.<N>.force_hw_error=1'. When a halt due to a channel error is detected, ioat(4) blocks new operations from being queued on the channel, completes any outstanding operations with an error status, and resets the channel before allowing new operations to be queued again. Update ioat.4 to document error recovery; document blockfill introduced in r290021 while we are here; document ioat_put_dmaengine() added in r289907; document DMA_NO_WAIT added in r289982. Sponsored by: EMC / Isilon Storage Division
538 lines
13 KiB
C
538 lines
13 KiB
C
/*-
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* Copyright (C) 2012 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/ioccom.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/stdarg.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/pmap.h>
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#include "ioat.h"
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#include "ioat_hw.h"
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#include "ioat_internal.h"
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#include "ioat_test.h"
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#ifndef time_after
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#define time_after(a,b) ((long)(b) - (long)(a) < 0)
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#endif
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MALLOC_DEFINE(M_IOAT_TEST, "ioat_test", "ioat test allocations");
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#define IOAT_MAX_BUFS 256
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struct test_transaction {
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void *buf[IOAT_MAX_BUFS];
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uint32_t length;
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uint32_t depth;
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struct ioat_test *test;
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TAILQ_ENTRY(test_transaction) entry;
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};
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#define IT_LOCK() mtx_lock(&ioat_test_lk)
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#define IT_UNLOCK() mtx_unlock(&ioat_test_lk)
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#define IT_ASSERT() mtx_assert(&ioat_test_lk, MA_OWNED)
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static struct mtx ioat_test_lk;
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MTX_SYSINIT(ioat_test_lk, &ioat_test_lk, "test coordination mtx", MTX_DEF);
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static int g_thread_index = 1;
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static struct cdev *g_ioat_cdev = NULL;
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#define ioat_test_log(v, ...) _ioat_test_log((v), "ioat_test: " __VA_ARGS__)
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static inline void _ioat_test_log(int verbosity, const char *fmt, ...);
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static void
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ioat_test_transaction_destroy(struct test_transaction *tx)
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{
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int i;
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for (i = 0; i < IOAT_MAX_BUFS; i++) {
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if (tx->buf[i] != NULL) {
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contigfree(tx->buf[i], tx->length, M_IOAT_TEST);
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tx->buf[i] = NULL;
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}
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}
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free(tx, M_IOAT_TEST);
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}
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static struct
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test_transaction *ioat_test_transaction_create(unsigned num_buffers,
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uint32_t buffer_size)
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{
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struct test_transaction *tx;
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unsigned i;
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tx = malloc(sizeof(*tx), M_IOAT_TEST, M_NOWAIT | M_ZERO);
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if (tx == NULL)
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return (NULL);
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tx->length = buffer_size;
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for (i = 0; i < num_buffers; i++) {
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tx->buf[i] = contigmalloc(buffer_size, M_IOAT_TEST, M_NOWAIT,
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0, BUS_SPACE_MAXADDR, PAGE_SIZE, 0);
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if (tx->buf[i] == NULL) {
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ioat_test_transaction_destroy(tx);
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return (NULL);
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}
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}
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return (tx);
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}
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static void
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dump_hex(void *p, size_t chunks)
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{
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size_t i, j;
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for (i = 0; i < chunks; i++) {
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for (j = 0; j < 8; j++)
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printf("%08x ", ((uint32_t *)p)[i * 8 + j]);
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printf("\n");
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}
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}
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static bool
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ioat_compare_ok(struct test_transaction *tx)
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{
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struct ioat_test *test;
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char *dst, *src;
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uint32_t i, j;
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test = tx->test;
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for (i = 0; i < tx->depth; i++) {
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dst = tx->buf[2 * i + 1];
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src = tx->buf[2 * i];
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if (test->testkind == IOAT_TEST_FILL) {
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for (j = 0; j < tx->length; j += sizeof(uint64_t)) {
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if (memcmp(src, &dst[j],
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MIN(sizeof(uint64_t), tx->length - j))
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!= 0)
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return (false);
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}
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} else if (test->testkind == IOAT_TEST_DMA) {
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if (memcmp(src, dst, tx->length) != 0)
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return (false);
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} else if (test->testkind == IOAT_TEST_RAW_DMA) {
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if (test->raw_write)
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dst = test->raw_vtarget;
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dump_hex(dst, tx->length / 32);
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}
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}
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return (true);
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}
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static void
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ioat_dma_test_callback(void *arg, int error)
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{
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struct test_transaction *tx;
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struct ioat_test *test;
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if (error != 0)
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ioat_test_log(0, "%s: Got error: %d\n", __func__, error);
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tx = arg;
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test = tx->test;
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if (test->verify && !ioat_compare_ok(tx)) {
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ioat_test_log(0, "miscompare found\n");
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atomic_add_32(&test->status[IOAT_TEST_MISCOMPARE], tx->depth);
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} else if (!test->too_late)
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atomic_add_32(&test->status[IOAT_TEST_OK], tx->depth);
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IT_LOCK();
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TAILQ_REMOVE(&test->pend_q, tx, entry);
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TAILQ_INSERT_TAIL(&test->free_q, tx, entry);
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wakeup(&test->free_q);
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IT_UNLOCK();
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}
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static int
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ioat_test_prealloc_memory(struct ioat_test *test, int index)
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{
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uint32_t i, j, k;
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struct test_transaction *tx;
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for (i = 0; i < test->transactions; i++) {
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tx = ioat_test_transaction_create(test->chain_depth * 2,
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test->buffer_size);
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if (tx == NULL) {
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ioat_test_log(0, "tx == NULL - memory exhausted\n");
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test->status[IOAT_TEST_NO_MEMORY]++;
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return (ENOMEM);
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}
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TAILQ_INSERT_HEAD(&test->free_q, tx, entry);
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tx->test = test;
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tx->depth = test->chain_depth;
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/* fill in source buffers */
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for (j = 0; j < (tx->length / sizeof(uint32_t)); j++) {
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uint32_t val = j + (index << 28);
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for (k = 0; k < test->chain_depth; k++) {
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((uint32_t *)tx->buf[2*k])[j] = ~val;
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((uint32_t *)tx->buf[2*k+1])[j] = val;
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}
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}
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}
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return (0);
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}
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static void
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ioat_test_release_memory(struct ioat_test *test)
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{
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struct test_transaction *tx, *s;
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TAILQ_FOREACH_SAFE(tx, &test->free_q, entry, s)
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ioat_test_transaction_destroy(tx);
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TAILQ_INIT(&test->free_q);
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TAILQ_FOREACH_SAFE(tx, &test->pend_q, entry, s)
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ioat_test_transaction_destroy(tx);
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TAILQ_INIT(&test->pend_q);
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}
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static void
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ioat_test_submit_1_tx(struct ioat_test *test, bus_dmaengine_t dma)
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{
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struct test_transaction *tx;
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struct bus_dmadesc *desc;
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bus_dmaengine_callback_t cb;
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bus_addr_t src, dest;
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uint64_t fillpattern;
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uint32_t i, flags;
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desc = NULL;
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IT_LOCK();
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while (TAILQ_EMPTY(&test->free_q))
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msleep(&test->free_q, &ioat_test_lk, 0, "test_submit", 0);
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tx = TAILQ_FIRST(&test->free_q);
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TAILQ_REMOVE(&test->free_q, tx, entry);
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TAILQ_INSERT_HEAD(&test->pend_q, tx, entry);
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IT_UNLOCK();
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ioat_acquire(dma);
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for (i = 0; i < tx->depth; i++) {
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src = vtophys((vm_offset_t)tx->buf[2*i]);
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dest = vtophys((vm_offset_t)tx->buf[2*i+1]);
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if (test->testkind == IOAT_TEST_RAW_DMA) {
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if (test->raw_write)
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dest = test->raw_target;
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else
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src = test->raw_target;
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}
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if (i == tx->depth - 1) {
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cb = ioat_dma_test_callback;
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flags = DMA_INT_EN;
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} else {
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cb = NULL;
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flags = 0;
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}
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if (test->testkind == IOAT_TEST_DMA ||
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test->testkind == IOAT_TEST_RAW_DMA)
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desc = ioat_copy(dma, dest, src, tx->length, cb, tx,
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flags);
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else if (test->testkind == IOAT_TEST_FILL) {
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fillpattern = *(uint64_t *)tx->buf[2*i];
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desc = ioat_blockfill(dma, dest, fillpattern,
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tx->length, cb, tx, flags);
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}
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if (desc == NULL)
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break;
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}
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ioat_release(dma);
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/*
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* We couldn't issue an IO -- either the device is being detached or
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* the HW reset. Essentially spin until the device comes back up or
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* our timer expires.
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*/
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if (desc == NULL && tx->depth > 0) {
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atomic_add_32(&test->status[IOAT_TEST_NO_DMA_ENGINE], tx->depth);
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IT_LOCK();
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TAILQ_REMOVE(&test->pend_q, tx, entry);
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TAILQ_INSERT_HEAD(&test->free_q, tx, entry);
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IT_UNLOCK();
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}
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}
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static void
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ioat_dma_test(void *arg)
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{
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struct ioat_test *test;
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bus_dmaengine_t dmaengine;
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uint32_t loops;
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int index, rc, start, end;
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test = arg;
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memset(__DEVOLATILE(void *, test->status), 0, sizeof(test->status));
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if (test->buffer_size > 1024 * 1024) {
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ioat_test_log(0, "Buffer size too large >1MB\n");
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test->status[IOAT_TEST_NO_MEMORY]++;
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return;
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}
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if (test->chain_depth * 2 > IOAT_MAX_BUFS) {
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ioat_test_log(0, "Depth too large (> %u)\n",
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(unsigned)IOAT_MAX_BUFS / 2);
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test->status[IOAT_TEST_NO_MEMORY]++;
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return;
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}
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if (btoc((uint64_t)test->buffer_size * test->chain_depth *
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test->transactions) > (physmem / 4)) {
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ioat_test_log(0, "Sanity check failed -- test would "
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"use more than 1/4 of phys mem.\n");
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test->status[IOAT_TEST_NO_MEMORY]++;
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return;
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}
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if ((uint64_t)test->transactions * test->chain_depth > (1<<16)) {
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ioat_test_log(0, "Sanity check failed -- test would "
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"use more than available IOAT ring space.\n");
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test->status[IOAT_TEST_NO_MEMORY]++;
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return;
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}
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if (test->testkind >= IOAT_NUM_TESTKINDS) {
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ioat_test_log(0, "Invalid kind %u\n",
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(unsigned)test->testkind);
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test->status[IOAT_TEST_INVALID_INPUT]++;
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return;
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}
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dmaengine = ioat_get_dmaengine(test->channel_index);
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if (dmaengine == NULL) {
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ioat_test_log(0, "Couldn't acquire dmaengine\n");
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test->status[IOAT_TEST_NO_DMA_ENGINE]++;
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return;
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}
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if (test->testkind == IOAT_TEST_FILL &&
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(to_ioat_softc(dmaengine)->capabilities & IOAT_DMACAP_BFILL) == 0)
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{
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ioat_test_log(0,
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"Hardware doesn't support block fill, aborting test\n");
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test->status[IOAT_TEST_INVALID_INPUT]++;
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goto out;
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}
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if (test->testkind == IOAT_TEST_RAW_DMA) {
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if (test->raw_is_virtual) {
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test->raw_vtarget = (void *)test->raw_target;
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test->raw_target = vtophys(test->raw_vtarget);
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} else {
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test->raw_vtarget = pmap_mapdev(test->raw_target,
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test->buffer_size);
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}
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}
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index = g_thread_index++;
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TAILQ_INIT(&test->free_q);
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TAILQ_INIT(&test->pend_q);
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if (test->duration == 0)
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ioat_test_log(1, "Thread %d: num_loops remaining: 0x%08x\n",
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index, test->transactions);
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else
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ioat_test_log(1, "Thread %d: starting\n", index);
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rc = ioat_test_prealloc_memory(test, index);
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if (rc != 0) {
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ioat_test_log(0, "prealloc_memory: %d\n", rc);
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goto out;
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}
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wmb();
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test->too_late = false;
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start = ticks;
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end = start + (((sbintime_t)test->duration * hz) / 1000);
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for (loops = 0;; loops++) {
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if (test->duration == 0 && loops >= test->transactions)
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break;
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else if (test->duration != 0 && time_after(ticks, end)) {
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test->too_late = true;
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break;
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}
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ioat_test_submit_1_tx(test, dmaengine);
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}
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ioat_test_log(1, "Test Elapsed: %d ticks (overrun %d), %d sec.\n",
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ticks - start, ticks - end, (ticks - start) / hz);
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IT_LOCK();
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while (!TAILQ_EMPTY(&test->pend_q))
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msleep(&test->free_q, &ioat_test_lk, 0, "ioattestcompl", hz);
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IT_UNLOCK();
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ioat_test_log(1, "Test Elapsed2: %d ticks (overrun %d), %d sec.\n",
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ticks - start, ticks - end, (ticks - start) / hz);
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ioat_test_release_memory(test);
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out:
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if (test->testkind == IOAT_TEST_RAW_DMA && !test->raw_is_virtual)
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pmap_unmapdev((vm_offset_t)test->raw_vtarget,
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test->buffer_size);
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ioat_put_dmaengine(dmaengine);
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}
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static int
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ioat_test_open(struct cdev *dev, int flags, int fmt, struct thread *td)
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{
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return (0);
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}
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static int
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ioat_test_close(struct cdev *dev, int flags, int fmt, struct thread *td)
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{
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return (0);
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}
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static int
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ioat_test_ioctl(struct cdev *dev, unsigned long cmd, caddr_t arg, int flag,
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struct thread *td)
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{
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switch (cmd) {
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case IOAT_DMATEST:
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ioat_dma_test(arg);
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break;
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default:
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return (EINVAL);
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}
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return (0);
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}
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static struct cdevsw ioat_cdevsw = {
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.d_version = D_VERSION,
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.d_flags = 0,
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.d_open = ioat_test_open,
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.d_close = ioat_test_close,
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.d_ioctl = ioat_test_ioctl,
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.d_name = "ioat_test",
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};
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static int
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enable_ioat_test(bool enable)
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{
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mtx_assert(&Giant, MA_OWNED);
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if (enable && g_ioat_cdev == NULL) {
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g_ioat_cdev = make_dev(&ioat_cdevsw, 0, UID_ROOT, GID_WHEEL,
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0600, "ioat_test");
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} else if (!enable && g_ioat_cdev != NULL) {
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destroy_dev(g_ioat_cdev);
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g_ioat_cdev = NULL;
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}
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return (0);
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}
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static int
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sysctl_enable_ioat_test(SYSCTL_HANDLER_ARGS)
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{
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int error, enabled;
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enabled = (g_ioat_cdev != NULL);
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error = sysctl_handle_int(oidp, &enabled, 0, req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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enable_ioat_test(enabled);
|
|
return (0);
|
|
}
|
|
SYSCTL_PROC(_hw_ioat, OID_AUTO, enable_ioat_test, CTLTYPE_INT | CTLFLAG_RW,
|
|
0, 0, sysctl_enable_ioat_test, "I",
|
|
"Non-zero: Enable the /dev/ioat_test device");
|
|
|
|
void
|
|
ioat_test_attach(void)
|
|
{
|
|
char *val;
|
|
|
|
val = kern_getenv("hw.ioat.enable_ioat_test");
|
|
if (val != NULL && strcmp(val, "0") != 0) {
|
|
mtx_lock(&Giant);
|
|
enable_ioat_test(true);
|
|
mtx_unlock(&Giant);
|
|
}
|
|
freeenv(val);
|
|
}
|
|
|
|
void
|
|
ioat_test_detach(void)
|
|
{
|
|
|
|
mtx_lock(&Giant);
|
|
enable_ioat_test(false);
|
|
mtx_unlock(&Giant);
|
|
}
|
|
|
|
static inline void
|
|
_ioat_test_log(int verbosity, const char *fmt, ...)
|
|
{
|
|
va_list argp;
|
|
|
|
if (verbosity > g_ioat_debug_level)
|
|
return;
|
|
|
|
va_start(argp, fmt);
|
|
vprintf(fmt, argp);
|
|
va_end(argp);
|
|
}
|