7bdcca7896
On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518
652 lines
16 KiB
C
652 lines
16 KiB
C
/*-
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* Copyright (c) 2007 Bruce M. Simpson.
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* Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
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* Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
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* Copyright (c) 2017 The FreeBSD Foundation
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* All rights reserved.
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*
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* Portions of this software were developed by Landon Fuller
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* under sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/imgact.h>
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#include <sys/bio.h>
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#include <sys/buf.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/cons.h>
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#include <sys/exec.h>
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#include <sys/ucontext.h>
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#include <sys/proc.h>
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#include <sys/kdb.h>
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#include <sys/ptrace.h>
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#include <sys/reboot.h>
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#include <sys/signalvar.h>
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#include <sys/sysent.h>
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#include <sys/sysproto.h>
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#include <sys/user.h>
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#include <vm/vm.h>
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#include <vm/vm_object.h>
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#include <vm/vm_page.h>
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#include <machine/cache.h>
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#include <machine/clock.h>
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#include <machine/cpu.h>
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#include <machine/cpuinfo.h>
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#include <machine/cpufunc.h>
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#include <machine/cpuregs.h>
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#include <machine/hwfunc.h>
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#include <machine/intr_machdep.h>
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#include <machine/locore.h>
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#include <machine/md_var.h>
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#include <machine/pte.h>
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#include <machine/sigframe.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#include <dev/bhnd/bhnd.h>
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#include <dev/bhnd/bhndreg.h>
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#include <dev/bhnd/bhnd_eromvar.h>
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#include <dev/bhnd/bcma/bcma_eromvar.h>
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#include <dev/bhnd/siba/sibareg.h>
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#include <dev/bhnd/siba/sibavar.h>
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#include <dev/bhnd/cores/chipc/chipcreg.h>
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#include <dev/bhnd/cores/pmu/bhnd_pmureg.h>
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#include "bcm_machdep.h"
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#include "bcm_bmips_exts.h"
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#ifdef CFE
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#include <dev/cfe/cfe_api.h>
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#include <dev/cfe/cfe_error.h>
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#endif
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#if 0
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#define BCM_TRACE(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
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#else
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#define BCM_TRACE(_fmt, ...)
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#endif
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static int bcm_init_platform_data(struct bcm_platform *bp);
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static int bcm_find_core(struct bcm_platform *bp,
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const struct bhnd_core_match *descs, size_t num_descs,
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struct bhnd_core_info *info, uintptr_t *addr);
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static int bcm_erom_probe_and_attach(bhnd_erom_class_t **erom_cls,
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kobj_ops_t erom_ops, bhnd_erom_t *erom, size_t esize,
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struct bhnd_erom_io *eio, struct bhnd_chipid *cid);
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extern int *edata;
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extern int *end;
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static struct bcm_platform bcm_platform_data;
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static bool bcm_platform_data_avail = false;
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#ifdef CFE
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static struct bcm_nvram_iocfe bcm_cfe_nvram;
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#endif
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static const struct bhnd_core_match bcm_chipc_cores[] = {
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{ BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_CC) },
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{ BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_4706_CC) },
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};
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static const struct bhnd_core_match bcm_cpu0_cores[] = {
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{
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BHND_MATCH_CORE_CLASS(BHND_DEVCLASS_CPU),
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BHND_MATCH_CORE_UNIT(0)
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}
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};
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static const struct bhnd_core_match bcm_pmu_cores[] = {
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{ BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_PMU) },
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};
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struct bcm_platform *
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bcm_get_platform(void)
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{
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if (!bcm_platform_data_avail)
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panic("platform data not available");
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return (&bcm_platform_data);
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}
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static bus_addr_t
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bcm_get_bus_addr(void)
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{
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long maddr;
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if (resource_long_value("bhnd", 0, "maddr", &maddr) == 0)
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return ((u_long)maddr);
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return (BHND_DEFAULT_CHIPC_ADDR);
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}
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static bus_size_t
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bcm_get_bus_size(void)
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{
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long msize;
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if (resource_long_value("bhnd", 0, "msize", &msize) == 0)
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return ((u_long)msize);
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return (BHND_DEFAULT_ENUM_SIZE);
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}
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/**
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* Search the device enumeration table for a core matching @p descs,
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*
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* @param bp Platform state containing a valid EROM parser.
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* @param descs The core match descriptor table.
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* @param num_descs The number of match descriptors in @p descs.
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* @param[out] info If non-NULL, will be populated with the core
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* info.
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* @param[out] addr If non-NULL, will be populated with the core's
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* physical register address.
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*/
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static int
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bcm_find_core(struct bcm_platform *bp, const struct bhnd_core_match *descs,
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size_t num_descs, struct bhnd_core_info *info, uintptr_t *addr)
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{
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bhnd_addr_t b_addr;
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bhnd_size_t b_size;
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int error;
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/* Fetch core info */
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for (size_t i = 0; i < num_descs; i++) {
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error = bhnd_erom_lookup_core_addr(&bp->erom.obj, &descs[i],
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BHND_PORT_DEVICE, 0, 0, info, &b_addr, &b_size);
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/* Terminate search on first match */
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if (error == 0)
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break;
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/* Terminate on first error (other than core not found) */
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if (error != ENOENT)
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return (error);
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/* Continue search ... */
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}
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/* Provide the core's base address */
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if (addr != NULL && b_addr > UINTPTR_MAX) {
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BCM_ERR("core address %#jx overflows native address width\n",
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(uintmax_t)b_addr);
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return (ERANGE);
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}
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if (addr != NULL)
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*addr = b_addr;
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return (0);
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}
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/**
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* Read a variable directly from NVRAM, decoding as @p type.
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*
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* @param bp Platform state.
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* @param name The raw name of the variable to be fetched,
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* including any device path (/pci/1/1/varname) or
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* alias prefix (0:varname).
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* @param[out] buf On success, the requested value will be written
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* to this buffer. This argment may be NULL if
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* the value is not desired.
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* @param[in,out] len The capacity of @p buf. On success, will be set
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* to the actual size of the requested value.
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* @param type The data type to be written to @p buf.
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*
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* @retval 0 success
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* @retval ENOMEM If @p buf is non-NULL and a buffer of @p len is too
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* small to hold the requested value.
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* @retval ENOENT If @p name is not found.
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* @retval EFTYPE If the variable data cannot be coerced to @p type.
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* @retval ERANGE If value coercion would overflow @p type.
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* @retval non-zero If parsing NVRAM otherwise fails, a regular unix error
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* code will be returned.
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*/
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int
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bcm_get_nvram(struct bcm_platform *bp, const char *name, void *buf, size_t *len,
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bhnd_nvram_type type)
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{
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if (bp->nvram_io == NULL || bp->nvram_cls == NULL)
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return (ENOENT);
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return (bhnd_nvram_data_getvar_direct(bp->nvram_cls, bp->nvram_io, name,
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buf, len, type));
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}
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/**
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* Probe and attach a bhnd_erom parser instance for the bhnd bus.
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*
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* @param[out] erom_cls The probed EROM class.
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* @param[out] erom_ops The storage to be used when compiling
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* @p erom_cls.
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* @param[out] erom The storage to be used when initializing the
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* static instance of @p erom_cls.
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* @param esize The total available number of bytes allocated
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* for @p erom. If this is less than is required
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* by @p erom_cls ENOMEM will be returned.
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* @param eio EROM I/O callbacks to be used.
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* @param[out] cid On success, the probed chip identification.
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*/
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static int
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bcm_erom_probe_and_attach(bhnd_erom_class_t **erom_cls, kobj_ops_t erom_ops,
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bhnd_erom_t *erom, size_t esize, struct bhnd_erom_io *eio,
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struct bhnd_chipid *cid)
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{
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bhnd_erom_class_t **clsp;
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bus_addr_t bus_addr;
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int error, prio, result;
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*erom_cls = NULL;
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prio = 0;
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/* Map our first bus core for the erom probe */
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bus_addr = bcm_get_bus_addr();
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if ((error = bhnd_erom_io_map(eio, bus_addr, BHND_DEFAULT_CORE_SIZE))) {
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BCM_ERR("failed to map first core at %#jx+%#jx: %d\n",
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(uintmax_t)bus_addr, (uintmax_t)BHND_DEFAULT_CORE_SIZE,
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error);
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return (error);
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}
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SET_FOREACH(clsp, bhnd_erom_class_set) {
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struct bhnd_chipid pcid;
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bhnd_erom_class_t *cls;
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struct kobj_ops kops;
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cls = *clsp;
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/* Compile the class' ops table */
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kobj_class_compile_static(cls, &kops);
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/* Probe the bus address */
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result = bhnd_erom_probe(cls, eio, NULL, &pcid);
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/* Drop pointer to stack allocated ops table */
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cls->ops = NULL;
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/* The parser did not match if an error was returned */
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if (result > 0)
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continue;
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/* Check for a new highest priority match */
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if (*erom_cls == NULL || result > prio) {
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prio = result;
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*cid = pcid;
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*erom_cls = cls;
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}
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/* Terminate immediately on BUS_PROBE_SPECIFIC */
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if (result == BUS_PROBE_SPECIFIC)
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break;
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}
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/* Valid EROM class probed? */
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if (*erom_cls == NULL) {
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BCM_ERR("no erom parser found for root bus at %#jx\n",
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(uintmax_t)bus_addr);
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return (ENOENT);
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}
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/* Using the provided storage, recompile the erom class ... */
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kobj_class_compile_static(*erom_cls, erom_ops);
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/* ... and initialize the erom parser instance */
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error = bhnd_erom_init_static(*erom_cls, erom, esize, cid, eio);
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return (error);
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}
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/**
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* Populate platform configuration data.
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*/
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static int
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bcm_init_platform_data(struct bcm_platform *bp)
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{
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bus_addr_t bus_addr, bus_size;
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bus_space_tag_t erom_bst;
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bus_space_handle_t erom_bsh;
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bool aob, pmu;
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int error;
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bus_addr = bcm_get_bus_addr();
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bus_size = bcm_get_bus_size();
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#ifdef CFE
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/* Fetch CFE console handle (if any). Must be initialized before
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* any calls to printf/early_putc. */
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if ((bp->cfe_console = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE)) < 0)
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bp->cfe_console = -1;
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/* Probe CFE NVRAM sources */
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bp->nvram_io = &bcm_cfe_nvram.io;
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error = bcm_nvram_find_cfedev(&bcm_cfe_nvram, &bp->nvram_cls);
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if (error) {
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bp->nvram_io = NULL;
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bp->nvram_cls = NULL;
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}
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#endif /* CFE */
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/* Probe and attach device table provider, populating our
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* chip identification */
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erom_bst = mips_bus_space_generic;
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erom_bsh = BCM_SOC_BSH(bus_addr, 0);
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error = bhnd_erom_iobus_init(&bp->erom_io, bus_addr, bus_size, erom_bst,
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erom_bsh);
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if (error) {
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BCM_ERR("failed to initialize erom I/O callbacks: %d\n", error);
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return (error);
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}
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error = bcm_erom_probe_and_attach(&bp->erom_impl, &bp->erom_ops,
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&bp->erom.obj, sizeof(bp->erom), &bp->erom_io.eio, &bp->cid);
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if (error) {
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BCM_ERR("error attaching erom parser: %d\n", error);
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bhnd_erom_io_fini(&bp->erom_io.eio);
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return (error);
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}
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if (bootverbose)
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bhnd_erom_dump(&bp->erom.obj);
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/* Fetch chipcommon core info */
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error = bcm_find_core(bp, bcm_chipc_cores, nitems(bcm_chipc_cores),
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&bp->cc_id, &bp->cc_addr);
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if (error) {
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BCM_ERR("error locating chipc core: %d\n", error);
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return (error);
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}
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/* Fetch chipc capability flags */
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bp->cc_caps = BCM_SOC_READ_4(bp->cc_addr, CHIPC_CAPABILITIES);
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bp->cc_caps_ext = 0x0;
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if (CHIPC_HWREV_HAS_CAP_EXT(bp->cc_id.hwrev))
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bp->cc_caps_ext = BCM_CHIPC_READ_4(bp, CHIPC_CAPABILITIES_EXT);
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/* Fetch PMU info */
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pmu = CHIPC_GET_FLAG(bp->cc_caps, CHIPC_CAP_PMU);
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aob = CHIPC_GET_FLAG(bp->cc_caps_ext, CHIPC_CAP2_AOB);
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if (pmu && aob) {
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/* PMU block mapped to a PMU core on the Always-on-Bus (aob) */
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error = bcm_find_core(bp, bcm_pmu_cores, nitems(bcm_pmu_cores),
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&bp->pmu_id, &bp->pmu_addr);
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if (error) {
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BCM_ERR("error locating pmu core: %d\n", error);
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return (error);
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}
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} else if (pmu) {
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/* PMU block mapped to chipc */
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bp->pmu_addr = bp->cc_addr;
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bp->pmu_id = bp->cc_id;
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} else {
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/* No PMU */
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bp->pmu_addr = 0x0;
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memset(&bp->pmu_id, 0, sizeof(bp->pmu_id));
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}
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/* Initialize PMU query state */
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if (pmu) {
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error = bhnd_pmu_query_init(&bp->pmu, NULL, bp->cid,
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&bcm_pmu_soc_io, bp);
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if (error) {
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BCM_ERR("bhnd_pmu_query_init() failed: %d\n", error);
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return (error);
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}
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}
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/* Find CPU core info */
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error = bcm_find_core(bp, bcm_cpu0_cores, nitems(bcm_cpu0_cores),
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&bp->cpu_id, &bp->cpu_addr);
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if (error) {
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BCM_ERR("error locating CPU core: %d\n", error);
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return (error);
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}
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/* Initialize our platform service registry */
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if ((error = bhnd_service_registry_init(&bp->services))) {
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BCM_ERR("error initializing service registry: %d\n", error);
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return (error);
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}
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bcm_platform_data_avail = true;
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return (0);
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}
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void
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platform_cpu_init()
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{
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/* Nothing special */
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}
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static void
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mips_init(void)
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{
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int i, j;
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printf("entry: mips_init()\n");
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#ifdef CFE
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/*
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* Query DRAM memory map from CFE.
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*/
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physmem = 0;
|
|
for (i = 0; i < 10; i += 2) {
|
|
int result;
|
|
uint64_t addr, len, type;
|
|
|
|
result = cfe_enummem(i / 2, 0, &addr, &len, &type);
|
|
if (result < 0) {
|
|
BCM_TRACE("There is no phys memory for: %d\n", i);
|
|
phys_avail[i] = phys_avail[i + 1] = 0;
|
|
break;
|
|
}
|
|
if (type != CFE_MI_AVAILABLE) {
|
|
BCM_TRACE("phys memory is not available: %d\n", i);
|
|
continue;
|
|
}
|
|
|
|
phys_avail[i] = addr;
|
|
if (i == 0 && addr == 0) {
|
|
/*
|
|
* If this is the first physical memory segment probed
|
|
* from CFE, omit the region at the start of physical
|
|
* memory where the kernel has been loaded.
|
|
*/
|
|
phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
|
|
}
|
|
|
|
BCM_TRACE("phys memory is available for: %d\n", i);
|
|
BCM_TRACE(" => addr = %jx\n", addr);
|
|
BCM_TRACE(" => len = %jd\n", len);
|
|
|
|
phys_avail[i + 1] = addr + len;
|
|
physmem += len;
|
|
}
|
|
|
|
BCM_TRACE("Total phys memory is : %ld\n", physmem);
|
|
realmem = btoc(physmem);
|
|
#endif
|
|
|
|
for (j = 0; j < i; j++)
|
|
dump_avail[j] = phys_avail[j];
|
|
|
|
physmem = realmem;
|
|
|
|
init_param1();
|
|
init_param2(physmem);
|
|
mips_cpu_init();
|
|
pmap_bootstrap();
|
|
mips_proc0_init();
|
|
mutex_init();
|
|
kdb_init();
|
|
#ifdef KDB
|
|
if (boothowto & RB_KDB)
|
|
kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
|
|
#endif
|
|
}
|
|
|
|
void
|
|
platform_reset(void)
|
|
{
|
|
struct bcm_platform *bp;
|
|
bool bcm4785war;
|
|
|
|
printf("bcm::platform_reset()\n");
|
|
intr_disable();
|
|
|
|
#ifdef CFE
|
|
/* Fall back on CFE if reset requested during platform
|
|
* data initialization */
|
|
if (!bcm_platform_data_avail) {
|
|
cfe_exit(0, 0);
|
|
while (1);
|
|
}
|
|
#endif
|
|
|
|
bp = bcm_get_platform();
|
|
bcm4785war = false;
|
|
|
|
/* Handle BCM4785-specific behavior */
|
|
if (bp->cid.chip_id == BHND_CHIPID_BCM4785) {
|
|
bcm4785war = true;
|
|
|
|
/* Switch to async mode */
|
|
bcm_bmips_wr_pllcfg3(BMIPS_BCMCFG_PLLCFG3_SM);
|
|
}
|
|
|
|
/* Set watchdog (PMU or ChipCommon) */
|
|
if (bp->pmu_addr != 0x0) {
|
|
BCM_PMU_WRITE_4(bp, BHND_PMU_WATCHDOG, 1);
|
|
} else
|
|
BCM_CHIPC_WRITE_4(bp, CHIPC_WATCHDOG, 1);
|
|
|
|
/* BCM4785 */
|
|
if (bcm4785war) {
|
|
mips_sync();
|
|
__asm __volatile("wait");
|
|
}
|
|
|
|
while (1);
|
|
}
|
|
|
|
void
|
|
platform_start(__register_t a0, __register_t a1, __register_t a2,
|
|
__register_t a3)
|
|
{
|
|
vm_offset_t kernend;
|
|
uint64_t platform_counter_freq;
|
|
int error;
|
|
|
|
/* clear the BSS and SBSS segments */
|
|
kernend = (vm_offset_t)&end;
|
|
memset(&edata, 0, kernend - (vm_offset_t)(&edata));
|
|
|
|
mips_postboot_fixup();
|
|
|
|
/* Initialize pcpu stuff */
|
|
mips_pcpu0_init();
|
|
|
|
#ifdef CFE
|
|
/*
|
|
* Initialize CFE firmware trampolines. This must be done
|
|
* before any CFE APIs are called, including writing
|
|
* to the CFE console.
|
|
*
|
|
* CFE passes the following values in registers:
|
|
* a0: firmware handle
|
|
* a2: firmware entry point
|
|
* a3: entry point seal
|
|
*/
|
|
if (a3 == CFE_EPTSEAL)
|
|
cfe_init(a0, a2);
|
|
#endif
|
|
|
|
/* Init BCM platform data */
|
|
if ((error = bcm_init_platform_data(&bcm_platform_data)))
|
|
panic("bcm_init_platform_data() failed: %d", error);
|
|
|
|
platform_counter_freq = bcm_get_cpufreq(bcm_get_platform());
|
|
|
|
/* CP0 ticks every two cycles */
|
|
mips_timer_early_init(platform_counter_freq / 2);
|
|
|
|
cninit();
|
|
|
|
mips_init();
|
|
|
|
mips_timer_init_params(platform_counter_freq, 1);
|
|
}
|
|
|
|
/*
|
|
* CFE-based EARLY_PRINTF support. To use, add the following to the kernel
|
|
* config:
|
|
* option EARLY_PRINTF
|
|
* option CFE
|
|
* device cfe
|
|
*/
|
|
#if defined(EARLY_PRINTF) && defined(CFE)
|
|
static void
|
|
bcm_cfe_eputc(int c)
|
|
{
|
|
unsigned char ch;
|
|
int handle;
|
|
|
|
ch = (unsigned char) c;
|
|
|
|
/* bcm_get_platform() cannot be used here, as we may be called
|
|
* from bcm_init_platform_data(). */
|
|
if ((handle = bcm_platform_data.cfe_console) < 0)
|
|
return;
|
|
|
|
if (ch == '\n')
|
|
early_putc('\r');
|
|
|
|
while ((cfe_write(handle, &ch, 1)) == 0)
|
|
continue;
|
|
}
|
|
|
|
early_putc_t *early_putc = bcm_cfe_eputc;
|
|
#endif /* EARLY_PRINTF */
|