5ba5b2308f
1. Define all registers. These definitions are needed to support
the FCM driver for direct-connect NAND.
2. Repurpose lbc_read_reg() and lbc_write_reg() for use by localbus
attached device drivers. Use bus_space functions directly in the
lbc driver itself.
3. Be smarter about programming LAWs and mapping memory. The ranges
defined in the FDT are per bank (= chip select) and since we can
have up to 8 banks, we could easily use more than 8 LAWs or TLB
enrties when per-bank memory ranges need multiple LAWs or TLBs
due to alignment or size constraints.
We now combine all memory ranges into the fewest possible set of
contiguous regions and program the hardware for that. Thus, a
cleverly written FDT with 8 devices may still only need 1 LAW or
1 TLB entry. Note that the memory ranges can be assigned randomly
to the banks. We sort as we build to handle that.
4. Support the FCM when programming the OR register. This is mostly
for documention purposes as we do not have a way to define the
mode for a bank.
5. Remove Semihalf-ism: do not define DEBUG (only to undefine it
again).
132 lines
4.7 KiB
C
132 lines
4.7 KiB
C
/*-
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* Copyright (c) 2006-2008, Juniper Networks, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_LBC_H_
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#define _MACHINE_LBC_H_
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/* Maximum number of devices on Local Bus */
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#define LBC_DEV_MAX 8
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/* Local access registers */
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#define LBC85XX_BR(n) (0x0 + (8 * n)) /* Base register 0-7 */
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#define LBC85XX_OR(n) (0x4 + (8 * n)) /* Options register 0-7 */
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#define LBC85XX_MAR 0x068 /* UPM address register */
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#define LBC85XX_MAMR 0x070 /* UPMA mode register */
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#define LBC85XX_MBMR 0x074 /* UPMB mode register */
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#define LBC85XX_MCMR 0x078 /* UPMC mode register */
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#define LBC85XX_MRTPR 0x084 /* Memory refresh timer prescaler */
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#define LBC85XX_MDR 0x088 /* UPM data register */
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#define LBC85XX_LSOR 0x090 /* Special operation initiation */
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#define LBC85XX_LURT 0x0a0 /* UPM refresh timer */
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#define LBC85XX_LSRT 0x0a4 /* SDRAM refresh timer */
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#define LBC85XX_LTESR 0x0b0 /* Transfer error status register */
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#define LBC85XX_LTEDR 0x0b4 /* Transfer error disable register */
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#define LBC85XX_LTEIR 0x0b8 /* Transfer error interrupt register */
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#define LBC85XX_LTEATR 0x0bc /* Transfer error attributes register */
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#define LBC85XX_LTEAR 0x0c0 /* Transfer error address register */
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#define LBC85XX_LTECCR 0x0c4 /* Transfer error ECC register */
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#define LBC85XX_LBCR 0x0d0 /* Configuration register */
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#define LBC85XX_LCRR 0x0d4 /* Clock ratio register */
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#define LBC85XX_FMR 0x0e0 /* Flash mode register */
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#define LBC85XX_FIR 0x0e4 /* Flash instruction register */
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#define LBC85XX_FCR 0x0e8 /* Flash command register */
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#define LBC85XX_FBAR 0x0ec /* Flash block address register */
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#define LBC85XX_FPAR 0x0f0 /* Flash page address register */
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#define LBC85XX_FBCR 0x0f4 /* Flash byte count register */
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#define LBC85XX_FECC0 0x100 /* Flash ECC block 0 register */
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#define LBC85XX_FECC1 0x104 /* Flash ECC block 0 register */
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#define LBC85XX_FECC2 0x108 /* Flash ECC block 0 register */
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#define LBC85XX_FECC3 0x10c /* Flash ECC block 0 register */
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/* LBC machine select */
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#define LBCRES_MSEL_GPCM 0
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#define LBCRES_MSEL_FCM 1
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#define LBCRES_MSEL_UPMA 8
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#define LBCRES_MSEL_UPMB 9
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#define LBCRES_MSEL_UPMC 10
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/* LBC data error checking modes */
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#define LBCRES_DECC_DISABLED 0
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#define LBCRES_DECC_NORMAL 1
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#define LBCRES_DECC_RMW 2
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/* LBC atomic operation modes */
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#define LBCRES_ATOM_DISABLED 0
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#define LBCRES_ATOM_RAWA 1
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#define LBCRES_ATOM_WARA 2
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struct lbc_memrange {
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vm_paddr_t addr;
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vm_size_t size;
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vm_offset_t kva;
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};
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struct lbc_bank {
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vm_paddr_t addr; /* physical addr of the bank */
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vm_size_t size; /* bank size */
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vm_offset_t kva; /* VA of the bank */
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/*
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* XXX the following bank attributes do not have properties specified
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* in the LBC DTS bindings yet (11.2009), so they are mainly a
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* placeholder for future extensions.
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*/
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int width; /* data bus width */
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uint8_t msel; /* machine select */
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uint8_t atom; /* atomic op mode */
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uint8_t wp; /* write protect */
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uint8_t decc; /* data error checking */
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};
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struct lbc_softc {
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device_t sc_dev;
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struct resource *sc_res;
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bus_space_handle_t sc_bsh;
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bus_space_tag_t sc_bst;
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int sc_rid;
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struct rman sc_rman;
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int sc_addr_cells;
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int sc_size_cells;
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struct lbc_memrange sc_range[LBC_DEV_MAX];
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struct lbc_bank sc_banks[LBC_DEV_MAX];
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};
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struct lbc_devinfo {
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struct ofw_bus_devinfo di_ofw;
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struct resource_list di_res;
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int di_bank;
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};
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uint32_t lbc_read_reg(device_t child, u_int off);
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void lbc_write_reg(device_t child, u_int off, uint32_t val);
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#endif /* _MACHINE_LBC_H_ */
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