be8d1ddc2e
with the INTR_FILTER-enabled MI code. Basically this consists of
registering an interrupt controller (of which there can be multiple
and optionally different ones either per host-to-foo bridge or shared
amongst host-to-foo bridges in any one machine) along with an interrupt
vector as specific argument for all the interrupt vectors used by a
given host-to-foo bridge (roughly similar to registering interrupt
sources on amd64 and i386), providing functions to enable, clear and
disable the interrupts of the children beneath the bridge.
This also includes:
- No longer entering a critical section in tl0_intr() and tl1_intr()
for executing interrupt handlers but rather let the handlers enter
it themselves so in the case of intr_event_handle() we don't enter
a nested critical section.
- Adding infrastructure for binding delivery of interrupt vectors to
specific CPUs which later on can be interfaced with the code from
amd64/i386 for binding interrupts to specific CPUs.
- Getting rid of the wrapper hack introduced along the lines of the
API changes for INTR_FILTER which as a side-effect caused interrupts
associated with ithread handlers only to get the elevated priority
of those associated with filters ("fast handlers") (this removes the
hack also in the non-INTR_FILTER case).
- Disabling (by not clearing) an interrupt in the interrupt controller
until all associated handlers have been executed, which is crucial
for the typical locking strategy of NIC drivers in order to work
correctly in case of shared interrupts. This was a more or less
theoretical problem on sparc64 though, as shared interrupts are
rather uncommon there except for the on-board SCCs and UARTs.
Note that due to the behavior of at least of some of the interrupt
controllers used on sparc64 an enable+EOI instead of a disable+EOI
approach (as implied by the INTR_FILTER MI code and implemented on
other architectures) is used as the latter can cause lost interrupts
or in the worst case interrupt starvation.
o Correct a typo in sbus_alloc_resource() which caused (pass-through)
allocations to only work down to the grandchildren of the bus, which
wasn't a real problem so far as we don't support any devices which are
great-grandchildren or greater of a U2S bridge, yet.
o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4()
in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid
of some other unneeded members in fhc_softc.
Reviewed by: marcel (earlier version)
Approved by: re (kensmith)
104 lines
3.0 KiB
C
104 lines
3.0 KiB
C
/*-
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* Copyright (c) 2001 Jake Burkholder.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_INTR_MACHDEP_H_
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#define _MACHINE_INTR_MACHDEP_H_
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#define IRSR_BUSY (1 << 5)
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#define PIL_MAX (1 << 4)
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#define IV_MAX (1 << 11)
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#define IV_NAMLEN 1024
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#define IR_FREE (PIL_MAX * 2)
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#define IH_SHIFT PTR_SHIFT
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#define IQE_SHIFT 5
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#define IV_SHIFT 6
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#define PIL_LOW 1 /* stray interrupts */
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#define PIL_ITHREAD 2 /* interrupts that use ithreads */
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#define PIL_RENDEZVOUS 3 /* smp rendezvous ipi */
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#define PIL_AST 4 /* ast ipi */
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#define PIL_STOP 5 /* stop cpu ipi */
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#define PIL_FAST 13 /* fast interrupts */
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#define PIL_TICK 14
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#ifndef LOCORE
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struct trapframe;
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typedef void ih_func_t(struct trapframe *);
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typedef void iv_func_t(void *);
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struct intr_request {
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struct intr_request *ir_next;
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iv_func_t *ir_func;
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void *ir_arg;
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u_int ir_vec;
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u_int ir_pri;
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};
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struct intr_controller {
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void (*ic_enable)(void *);
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void (*ic_disable)(void *);
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void (*ic_eoi)(void *);
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};
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struct intr_vector {
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iv_func_t *iv_func;
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void *iv_arg;
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const struct intr_controller *iv_ic;
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void *iv_icarg;
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struct intr_event *iv_event;
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u_int iv_pri;
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u_int iv_vec;
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u_int iv_mid;
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u_int iv_refcnt;
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u_int iv_pad[2];
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};
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extern ih_func_t *intr_handlers[];
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extern struct intr_vector intr_vectors[];
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void intr_setup(int level, ih_func_t *ihf, int pri, iv_func_t *ivf,
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void *iva);
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void intr_init1(void);
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void intr_init2(void);
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int intr_controller_register(int vec, const struct intr_controller *ic,
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void *icarg);
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int inthand_add(const char *name, int vec, int (*filt)(void *),
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void (*handler)(void *), void *arg, int flags, void **cookiep);
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int inthand_remove(int vec, void *cookie);
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ih_func_t intr_fast;
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#endif /* !LOCORE */
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#endif /* !_MACHINE_INTR_MACHDEP_H_ */
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