49 lines
3.2 KiB
LLVM
49 lines
3.2 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
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; arm64 has a separate copy due to intrinsics
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define <4 x i32> @copyTuple.QPair(i32* %a, i32* %b) {
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; CHECK-LABEL: copyTuple.QPair:
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; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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; CHECK: ld2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}]
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entry:
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%vld = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>, i64 1, i32* %a)
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%extract = extractvalue { <4 x i32>, <4 x i32> } %vld, 0
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%vld1 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32> %extract, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, i64 1, i32* %b)
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%vld1.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld1, 0
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ret <4 x i32> %vld1.fca.0.extract
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}
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define <4 x i32> @copyTuple.QTriple(i32* %a, i32* %b, <4 x i32> %c) {
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; CHECK-LABEL: copyTuple.QTriple:
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; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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; CHECK: ld3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}]
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entry:
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%vld = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, i64 1, i32* %a)
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%extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld, 0
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%vld1 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x i32> %extract, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, i64 1, i32* %b)
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%vld1.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld1, 0
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ret <4 x i32> %vld1.fca.0.extract
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}
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define <4 x i32> @copyTuple.QQuad(i32* %a, i32* %b, <4 x i32> %c) {
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; CHECK-LABEL: copyTuple.QQuad:
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; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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; CHECK: ld4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}]
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entry:
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%vld = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0i32(<4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, <4 x i32> %c, i64 1, i32* %a)
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%extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %vld, 0
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%vld1 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0i32(<4 x i32> %extract, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, i64 1, i32* %b)
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%vld1.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %vld1, 0
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ret <4 x i32> %vld1.fca.0.extract
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}
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declare { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32>, <4 x i32>, i64, i32*)
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declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, i64, i32*)
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declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i64, i32*)
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