564 lines
17 KiB
C
564 lines
17 KiB
C
/*-
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* Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*$FreeBSD$*/
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#include "opt_ddb.h"
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#include "opt_inet.h"
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#include "opt_inet6.h"
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#ifdef HAVE_KERNEL_OPTION_HEADERS
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#include "opt_device_polling.h"
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#endif
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#include <sys/param.h>
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#include <sys/systm.h>
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#ifdef DDB
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#include <sys/types.h>
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#include <ddb/ddb.h>
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#endif
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#if __FreeBSD_version >= 800000
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#include <sys/buf_ring.h>
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#endif
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/malloc.h>
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#include <sys/mbuf.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/smp.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <sys/eventhandler.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <net/bpf.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/if_arp.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/iflib.h>
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#include <net/if_types.h>
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#include <net/if_vlan_var.h>
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#include <netinet/in_systm.h>
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#include <netinet/ip.h>
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#include <netinet/ip6.h>
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#include <netinet/tcp.h>
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#include <netinet/udp.h>
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#include <machine/in_cksum.h>
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#include <dev/led/led.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include "e1000_api.h"
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#include "e1000_82571.h"
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#include "ifdi_if.h"
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#ifndef _EM_H_DEFINED_
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#define _EM_H_DEFINED_
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/* Tunables */
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/*
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* EM_TXD: Maximum number of Transmit Descriptors
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* Valid Range: 80-256 for 82542 and 82543-based adapters
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* 80-4096 for others
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* Default Value: 256
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* This value is the number of transmit descriptors allocated by the driver.
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* Increasing this value allows the driver to queue more transmits. Each
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* descriptor is 16 bytes.
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* Since TDLEN should be multiple of 128bytes, the number of transmit
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* desscriptors should meet the following condition.
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* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
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*/
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#define EM_MIN_TXD 128
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#define EM_MAX_TXD 4096
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#define EM_DEFAULT_TXD 1024
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#define EM_DEFAULT_MULTI_TXD 4096
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/*
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* EM_RXD - Maximum number of receive Descriptors
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* Valid Range: 80-256 for 82542 and 82543-based adapters
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* 80-4096 for others
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* Default Value: 256
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* This value is the number of receive descriptors allocated by the driver.
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* Increasing this value allows the driver to buffer more incoming packets.
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* Each descriptor is 16 bytes. A receive buffer is also allocated for each
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* descriptor. The maximum MTU size is 16110.
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* Since TDLEN should be multiple of 128bytes, the number of transmit
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* desscriptors should meet the following condition.
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* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
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*/
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#define EM_MIN_RXD 128
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#define EM_MAX_RXD 4096
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#define EM_DEFAULT_RXD 1024
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#define EM_DEFAULT_MULTI_RXD 4096
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/*
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* EM_TIDV - Transmit Interrupt Delay Value
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value delays the generation of transmit interrupts in units of
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* 1.024 microseconds. Transmit interrupt reduction can improve CPU
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* efficiency if properly tuned for specific network traffic. If the
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* system is reporting dropped transmits, this value may be set too high
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* causing the driver to run out of available transmit descriptors.
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*/
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#define EM_TIDV 64
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/*
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* EM_TADV - Transmit Absolute Interrupt Delay Value
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* (Not valid for 82542/82543/82544)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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* transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
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* this value ensures that an interrupt is generated after the initial
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* packet is sent on the wire within the set amount of time. Proper tuning,
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* along with EM_TIDV, may improve traffic throughput in specific
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* network conditions.
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*/
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#define EM_TADV 64
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/*
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* EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 0
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* This value delays the generation of receive interrupts in units of 1.024
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* microseconds. Receive interrupt reduction can improve CPU efficiency if
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* properly tuned for specific network traffic. Increasing this value adds
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* extra latency to frame reception and can end up decreasing the throughput
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* of TCP traffic. If the system is reporting dropped receives, this value
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* may be set too high, causing the driver to run out of available receive
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* descriptors.
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*
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* CAUTION: When setting EM_RDTR to a value other than 0, adapters
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* may hang (stop transmitting) under certain network conditions.
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* If this occurs a WATCHDOG message is logged in the system
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* event log. In addition, the controller is automatically reset,
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* restoring the network connection. To eliminate the potential
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* for the hang ensure that EM_RDTR is set to 0.
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*/
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#define EM_RDTR 0
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/*
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* Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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* receive interrupt is generated. Useful only if EM_RDTR is non-zero,
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* this value ensures that an interrupt is generated after the initial
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* packet is received within the set amount of time. Proper tuning,
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* along with EM_RDTR, may improve traffic throughput in specific network
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* conditions.
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*/
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#define EM_RADV 64
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/*
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* This parameter controls whether or not autonegotation is enabled.
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* 0 - Disable autonegotiation
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* 1 - Enable autonegotiation
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*/
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#define DO_AUTO_NEG 1
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/*
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* This parameter control whether or not the driver will wait for
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* autonegotiation to complete.
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* 1 - Wait for autonegotiation to complete
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* 0 - Don't wait for autonegotiation to complete
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*/
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#define WAIT_FOR_AUTO_NEG_DEFAULT 0
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/* Tunables -- End */
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#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
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ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
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ADVERTISE_1000_FULL)
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#define AUTO_ALL_MODES 0
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/* PHY master/slave setting */
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#define EM_MASTER_SLAVE e1000_ms_hw_default
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/*
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* Micellaneous constants
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*/
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#define EM_VENDOR_ID 0x8086
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#define EM_FLASH 0x0014
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#define EM_JUMBO_PBA 0x00000028
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#define EM_DEFAULT_PBA 0x00000030
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#define EM_SMARTSPEED_DOWNSHIFT 3
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#define EM_SMARTSPEED_MAX 15
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#define EM_MAX_LOOP 10
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#define MAX_NUM_MULTICAST_ADDRESSES 128
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#define PCI_ANY_ID (~0U)
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#define ETHER_ALIGN 2
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#define EM_FC_PAUSE_TIME 0x0680
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#define EM_EEPROM_APME 0x400;
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#define EM_82544_APME 0x0004;
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/* Support AutoMediaDetect for Marvell M88 PHY in i354 */
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#define IGB_MEDIA_RESET (1 << 0)
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/* Define the starting Interrupt rate per Queue */
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#define IGB_INTS_PER_SEC 8000
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#define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2)
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#define IGB_LINK_ITR 2000
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#define I210_LINK_DELAY 1000
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#define IGB_MAX_SCATTER 40
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#define IGB_VFTA_SIZE 128
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#define IGB_BR_SIZE 4096 /* ring buf size */
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#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
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#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */
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#define IGB_TXPBSIZE 20408
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#define IGB_HDR_BUF 128
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#define IGB_PKTTYPE_MASK 0x0000FFF0
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#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */
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/*
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* Driver state logic for the detection of a hung state
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* in hardware. Set TX_HUNG whenever a TX packet is used
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* (data is sent) and clear it when txeof() is invoked if
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* any descriptors from the ring are cleaned/reclaimed.
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* Increment internal counter if no descriptors are cleaned
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* and compare to TX_MAXTRIES. When counter > TX_MAXTRIES,
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* reset adapter.
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*/
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#define EM_TX_IDLE 0x00000000
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#define EM_TX_BUSY 0x00000001
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#define EM_TX_HUNG 0x80000000
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#define EM_TX_MAXTRIES 10
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#define PCICFG_DESC_RING_STATUS 0xe4
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#define FLUSH_DESC_REQUIRED 0x100
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#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \
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((hw->mac.type <= e1000_82576) ? 16 : 8))
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#define IGB_RX_HTHRESH 8
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#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
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(adapter->intr_type == IFLIB_INTR_MSIX)) ? 1 : 4)
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#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
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#define IGB_TX_HTHRESH 1
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#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \
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(adapter->intr_type == IFLIB_INTR_MSIX) ? 1 : 16)
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/*
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* TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
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* multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
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* also optimize cache line size effect. H/W supports up to cache line size 128.
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*/
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#define EM_DBA_ALIGN 128
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/*
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* See Intel 82574 Driver Programming Interface Manual, Section 10.2.6.9
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*/
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#define TARC_COMPENSATION_MODE (1 << 7) /* Compensation Mode */
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#define TARC_SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */
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#define TARC_MQ_FIX (1 << 23) | \
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(1 << 24) | \
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(1 << 25) /* Handle errata in MQ mode */
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#define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */
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/* PCI Config defines */
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#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
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#define EM_BAR_TYPE_MASK 0x00000001
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#define EM_BAR_TYPE_MMEM 0x00000000
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#define EM_BAR_TYPE_IO 0x00000001
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#define EM_BAR_TYPE_FLASH 0x0014
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#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
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#define EM_BAR_MEM_TYPE_MASK 0x00000006
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#define EM_BAR_MEM_TYPE_32BIT 0x00000000
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#define EM_BAR_MEM_TYPE_64BIT 0x00000004
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#define EM_MSIX_BAR 3 /* On 82575 */
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/* More backward compatibility */
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#if __FreeBSD_version < 900000
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#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
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#endif
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/* Defines for printing debug information */
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#define DEBUG_INIT 0
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#define DEBUG_IOCTL 0
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#define DEBUG_HW 0
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#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
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#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
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#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
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#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
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#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
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#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
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#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
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#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
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#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
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#define EM_MAX_SCATTER 40
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#define EM_VFTA_SIZE 128
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#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
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#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
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#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
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#define EM_MSIX_LINK 0x01000000 /* For 82574 use */
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#define ETH_ZLEN 60
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#define ETH_ADDR_LEN 6
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#define EM_CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
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#define IGB_CSUM_OFFLOAD 0x0E0F /* Offload bits in mbuf flag */
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#define IGB_PKTTYPE_MASK 0x0000FFF0
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#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */
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/*
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* 82574 has a nonstandard address for EIAC
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* and since its only used in MSIX, and in
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* the em driver only 82574 uses MSIX we can
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* solve it just using this define.
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*/
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#define EM_EIAC 0x000DC
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/*
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* 82574 only reports 3 MSI-X vectors by default;
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* defines assisting with making it report 5 are
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* located here.
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*/
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#define EM_NVM_PCIE_CTRL 0x1B
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#define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT)
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#define EM_NVM_MSIX_N_SHIFT 7
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struct adapter;
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struct em_int_delay_info {
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struct adapter *adapter; /* Back-pointer to the adapter struct */
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int offset; /* Register offset to read/write */
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int value; /* Current value in usecs */
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};
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/*
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* The transmit ring, one per tx queue
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*/
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struct tx_ring {
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struct adapter *adapter;
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struct e1000_tx_desc *tx_base;
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uint64_t tx_paddr;
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qidx_t *tx_rsq;
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bool tx_tso; /* last tx was tso */
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uint8_t me;
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qidx_t tx_rs_cidx;
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qidx_t tx_rs_pidx;
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qidx_t tx_cidx_processed;
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/* Interrupt resources */
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void *tag;
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struct resource *res;
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unsigned long tx_irq;
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/* Saved csum offloading context information */
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int csum_flags;
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int csum_lhlen;
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int csum_iphlen;
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int csum_thlen;
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int csum_mss;
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int csum_pktlen;
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uint32_t csum_txd_upper;
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uint32_t csum_txd_lower; /* last field */
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};
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/*
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* The Receive ring, one per rx queue
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*/
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struct rx_ring {
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struct adapter *adapter;
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struct em_rx_queue *que;
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u32 me;
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u32 payload;
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union e1000_rx_desc_extended *rx_base;
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uint64_t rx_paddr;
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/* Interrupt resources */
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void *tag;
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struct resource *res;
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bool discard;
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/* Soft stats */
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unsigned long rx_irq;
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unsigned long rx_discarded;
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unsigned long rx_packets;
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unsigned long rx_bytes;
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};
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struct em_tx_queue {
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struct adapter *adapter;
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u32 msix;
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u32 eims; /* This queue's EIMS bit */
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u32 me;
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struct tx_ring txr;
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};
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struct em_rx_queue {
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struct adapter *adapter;
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u32 me;
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u32 msix;
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u32 eims;
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struct rx_ring rxr;
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u64 irqs;
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struct if_irq que_irq;
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};
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/* Our adapter structure */
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struct adapter {
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struct ifnet *ifp;
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struct e1000_hw hw;
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if_softc_ctx_t shared;
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if_ctx_t ctx;
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#define tx_num_queues shared->isc_ntxqsets
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#define rx_num_queues shared->isc_nrxqsets
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#define intr_type shared->isc_intr
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/* FreeBSD operating-system-specific structures. */
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struct e1000_osdep osdep;
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device_t dev;
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struct cdev *led_dev;
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struct em_tx_queue *tx_queues;
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struct em_rx_queue *rx_queues;
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struct if_irq irq;
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struct resource *memory;
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struct resource *flash;
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struct resource *ioport;
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int io_rid;
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struct resource *res;
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void *tag;
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u32 linkvec;
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u32 ivars;
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struct ifmedia *media;
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int msix;
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int if_flags;
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int em_insert_vlan_header;
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u32 ims;
|
|
bool in_detach;
|
|
|
|
u32 flags;
|
|
/* Task for FAST handling */
|
|
struct grouptask link_task;
|
|
|
|
u16 num_vlans;
|
|
u32 txd_cmd;
|
|
|
|
u32 tx_process_limit;
|
|
u32 rx_process_limit;
|
|
u32 rx_mbuf_sz;
|
|
|
|
/* Management and WOL features */
|
|
u32 wol;
|
|
bool has_manage;
|
|
bool has_amt;
|
|
|
|
/* Multicast array memory */
|
|
u8 *mta;
|
|
|
|
/*
|
|
** Shadow VFTA table, this is needed because
|
|
** the real vlan filter table gets cleared during
|
|
** a soft reset and the driver needs to be able
|
|
** to repopulate it.
|
|
*/
|
|
u32 shadow_vfta[EM_VFTA_SIZE];
|
|
|
|
/* Info about the interface */
|
|
u16 link_active;
|
|
u16 fc;
|
|
u16 link_speed;
|
|
u16 link_duplex;
|
|
u32 smartspeed;
|
|
u32 dmac;
|
|
int link_mask;
|
|
|
|
u64 que_mask;
|
|
|
|
|
|
struct em_int_delay_info tx_int_delay;
|
|
struct em_int_delay_info tx_abs_int_delay;
|
|
struct em_int_delay_info rx_int_delay;
|
|
struct em_int_delay_info rx_abs_int_delay;
|
|
struct em_int_delay_info tx_itr;
|
|
|
|
/* Misc stats maintained by the driver */
|
|
unsigned long dropped_pkts;
|
|
unsigned long link_irq;
|
|
unsigned long mbuf_defrag_failed;
|
|
unsigned long no_tx_dma_setup;
|
|
unsigned long no_tx_map_avail;
|
|
unsigned long rx_overruns;
|
|
unsigned long watchdog_events;
|
|
|
|
struct e1000_hw_stats stats;
|
|
u16 vf_ifp;
|
|
};
|
|
|
|
/********************************************************************************
|
|
* vendor_info_array
|
|
*
|
|
* This array contains the list of Subvendor/Subdevice IDs on which the driver
|
|
* should load.
|
|
*
|
|
********************************************************************************/
|
|
typedef struct _em_vendor_info_t {
|
|
unsigned int vendor_id;
|
|
unsigned int device_id;
|
|
unsigned int subvendor_id;
|
|
unsigned int subdevice_id;
|
|
unsigned int index;
|
|
} em_vendor_info_t;
|
|
|
|
void em_dump_rs(struct adapter *);
|
|
|
|
#define EM_RSSRK_SIZE 4
|
|
#define EM_RSSRK_VAL(key, i) (key[(i) * EM_RSSRK_SIZE] | \
|
|
key[(i) * EM_RSSRK_SIZE + 1] << 8 | \
|
|
key[(i) * EM_RSSRK_SIZE + 2] << 16 | \
|
|
key[(i) * EM_RSSRK_SIZE + 3] << 24)
|
|
#endif /* _EM_H_DEFINED_ */
|