6f37f2324d
These include standalone X550 adapters, X552 10GbE backplane, and X552/X557-AT 10GBASE-T; with the latter two being integrated into Xeon D SoCs. As well, this bumps the ixgbe version number to 2.8.3, and includes updates to shared code for support for the new devices. Differential Revision: D2414 Reviewed by: gnn, adrian Approved by: jfv (mentor), gnn (mentor)
176 lines
6.2 KiB
C
176 lines
6.2 KiB
C
/******************************************************************************
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Copyright (c) 2001-2015, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _IXGBE_DCB_H_
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#define _IXGBE_DCB_H_
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#include "ixgbe_type.h"
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/* DCB defines */
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/* DCB credit calculation defines */
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#define IXGBE_DCB_CREDIT_QUANTUM 64
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#define IXGBE_DCB_MAX_CREDIT_REFILL 200 /* 200 * 64B = 12800B */
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#define IXGBE_DCB_MAX_TSO_SIZE (32 * 1024) /* Max TSO pkt size in DCB*/
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#define IXGBE_DCB_MAX_CREDIT (2 * IXGBE_DCB_MAX_CREDIT_REFILL)
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/* 513 for 32KB TSO packet */
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#define IXGBE_DCB_MIN_TSO_CREDIT \
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((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1)
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/* DCB configuration defines */
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#define IXGBE_DCB_MAX_USER_PRIORITY 8
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#define IXGBE_DCB_MAX_BW_GROUP 8
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#define IXGBE_DCB_BW_PERCENT 100
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#define IXGBE_DCB_TX_CONFIG 0
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#define IXGBE_DCB_RX_CONFIG 1
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/* DCB capability defines */
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#define IXGBE_DCB_PG_SUPPORT 0x00000001
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#define IXGBE_DCB_PFC_SUPPORT 0x00000002
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#define IXGBE_DCB_BCN_SUPPORT 0x00000004
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#define IXGBE_DCB_UP2TC_SUPPORT 0x00000008
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#define IXGBE_DCB_GSP_SUPPORT 0x00000010
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struct ixgbe_dcb_support {
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u32 capabilities; /* DCB capabilities */
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/* Each bit represents a number of TCs configurable in the hw.
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* If 8 traffic classes can be configured, the value is 0x80. */
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u8 traffic_classes;
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u8 pfc_traffic_classes;
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};
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enum ixgbe_dcb_tsa {
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ixgbe_dcb_tsa_ets = 0,
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ixgbe_dcb_tsa_group_strict_cee,
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ixgbe_dcb_tsa_strict
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};
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/* Traffic class bandwidth allocation per direction */
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struct ixgbe_dcb_tc_path {
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u8 bwg_id; /* Bandwidth Group (BWG) ID */
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u8 bwg_percent; /* % of BWG's bandwidth */
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u8 link_percent; /* % of link bandwidth */
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u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */
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u16 data_credits_refill; /* Credit refill amount in 64B granularity */
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u16 data_credits_max; /* Max credits for a configured packet buffer
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* in 64B granularity.*/
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enum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */
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};
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enum ixgbe_dcb_pfc {
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ixgbe_dcb_pfc_disabled = 0,
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ixgbe_dcb_pfc_enabled,
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ixgbe_dcb_pfc_enabled_txonly,
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ixgbe_dcb_pfc_enabled_rxonly
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};
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/* Traffic class configuration */
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struct ixgbe_dcb_tc_config {
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struct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */
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enum ixgbe_dcb_pfc pfc; /* Class based flow control setting */
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u16 desc_credits_max; /* For Tx Descriptor arbitration */
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u8 tc; /* Traffic class (TC) */
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};
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enum ixgbe_dcb_pba {
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/* PBA[0-7] each use 64KB FIFO */
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ixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL,
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/* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
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ixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED
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};
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struct ixgbe_dcb_num_tcs {
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u8 pg_tcs;
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u8 pfc_tcs;
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};
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struct ixgbe_dcb_config {
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struct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS];
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struct ixgbe_dcb_support support;
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struct ixgbe_dcb_num_tcs num_tcs;
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u8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */
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bool pfc_mode_enable;
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bool round_robin_enable;
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enum ixgbe_dcb_pba rx_pba_cfg;
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u32 dcb_cfg_version; /* Not used...OS-specific? */
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u32 link_speed; /* For bandwidth allocation validation purpose */
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bool vt_mode;
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};
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/* DCB driver APIs */
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/* DCB rule checking */
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s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *);
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/* DCB credits calculation */
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s32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int);
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s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *,
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struct ixgbe_dcb_config *, u32, u8);
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/* DCB PFC */
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s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *);
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s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);
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/* DCB stats */
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s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *);
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s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);
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s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);
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/* DCB config arbiters */
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s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *,
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struct ixgbe_dcb_config *);
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s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *,
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struct ixgbe_dcb_config *);
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s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *,
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struct ixgbe_dcb_config *);
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/* DCB unpack routines */
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void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *);
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void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *, int, u16 *);
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void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *, u16 *);
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void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *);
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void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *);
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void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *);
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u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8);
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/* DCB initialization */
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s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *);
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s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);
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#endif /* _IXGBE_DCB_H_ */
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