704bf01027
tree based on heuristics to parsing it based on the spec. This should also lay the foundation for NEW_PCIB on PowerPC. MFC after: 3 months
259 lines
6.3 KiB
C
259 lines
6.3 KiB
C
/*-
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* Copyright (C) 2002 Benno Rice.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <machine/bus.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/pio.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <powerpc/ofw/ofw_pci.h>
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#include <powerpc/powermac/uninorthvar.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include "pcib_if.h"
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#define UNINORTH_DEBUG 0
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/*
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* Device interface.
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*/
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static int uninorth_probe(device_t);
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static int uninorth_attach(device_t);
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/*
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* pcib interface.
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*/
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static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int,
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u_int, int);
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static void uninorth_write_config(device_t, u_int, u_int, u_int,
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u_int, u_int32_t, int);
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/*
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* Local routines.
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*/
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static int uninorth_enable_config(struct uninorth_softc *, u_int,
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u_int, u_int, u_int);
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/*
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* Driver methods.
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*/
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static device_method_t uninorth_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, uninorth_probe),
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DEVMETHOD(device_attach, uninorth_attach),
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/* pcib interface */
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DEVMETHOD(pcib_read_config, uninorth_read_config),
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DEVMETHOD(pcib_write_config, uninorth_write_config),
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DEVMETHOD_END
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};
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static devclass_t uninorth_devclass;
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DEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods,
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sizeof(struct uninorth_softc), ofw_pci_driver);
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DRIVER_MODULE(uninorth, nexus, uninorth_driver, uninorth_devclass, 0, 0);
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static int
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uninorth_probe(device_t dev)
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{
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const char *type, *compatible;
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type = ofw_bus_get_type(dev);
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compatible = ofw_bus_get_compat(dev);
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if (type == NULL || compatible == NULL)
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return (ENXIO);
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if (strcmp(type, "pci") != 0)
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return (ENXIO);
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if (strcmp(compatible, "uni-north") == 0) {
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device_set_desc(dev, "Apple UniNorth Host-PCI bridge");
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return (0);
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} else if (strcmp(compatible, "u3-agp") == 0) {
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device_set_desc(dev, "Apple U3 Host-AGP bridge");
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return (0);
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} else if (strcmp(compatible, "u4-pcie") == 0) {
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device_set_desc(dev, "IBM CPC945 PCI Express Root");
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return (0);
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}
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return (ENXIO);
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}
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static int
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uninorth_attach(device_t dev)
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{
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struct uninorth_softc *sc;
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const char *compatible;
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phandle_t node;
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u_int32_t reg[3];
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node = ofw_bus_get_node(dev);
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sc = device_get_softc(dev);
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if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
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return (ENXIO);
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sc->sc_ver = 0;
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compatible = ofw_bus_get_compat(dev);
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if (strcmp(compatible, "u3-agp") == 0)
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sc->sc_ver = 3;
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if (strcmp(compatible, "u4-pcie") == 0)
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sc->sc_ver = 4;
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if (sc->sc_ver >= 3) {
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sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[1] + 0x800000, PAGE_SIZE);
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sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1] + 0xc00000, PAGE_SIZE);
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} else {
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sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[0] + 0x800000, PAGE_SIZE);
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sc->sc_data = (vm_offset_t)pmap_mapdev(reg[0] + 0xc00000, PAGE_SIZE);
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}
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return (ofw_pci_attach(dev));
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}
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static u_int32_t
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uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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int width)
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{
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struct uninorth_softc *sc;
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vm_offset_t caoff;
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sc = device_get_softc(dev);
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caoff = sc->sc_data + (reg & 0x07);
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if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) {
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switch (width) {
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case 1:
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return (in8rb(caoff));
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break;
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case 2:
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return (in16rb(caoff));
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break;
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case 4:
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return (in32rb(caoff));
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break;
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}
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}
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return (0xffffffff);
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}
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static void
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uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, u_int32_t val, int width)
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{
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struct uninorth_softc *sc;
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vm_offset_t caoff;
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sc = device_get_softc(dev);
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caoff = sc->sc_data + (reg & 0x07);
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if (uninorth_enable_config(sc, bus, slot, func, reg)) {
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switch (width) {
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case 1:
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out8rb(caoff, val);
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break;
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case 2:
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out16rb(caoff, val);
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break;
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case 4:
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out32rb(caoff, val);
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break;
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}
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}
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}
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static int
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uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot,
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u_int func, u_int reg)
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{
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uint32_t cfgval;
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uint32_t pass;
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if (resource_int_value(device_get_name(sc->pci_sc.sc_dev),
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device_get_unit(sc->pci_sc.sc_dev), "skipslot", &pass) == 0) {
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if (pass == slot)
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return (0);
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}
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/*
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* Issue type 0 configuration space accesses for the root bus.
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*
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* NOTE: On U4, issue only type 1 accesses. There is a secret
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* PCI Express <-> PCI Express bridge not present in the device tree,
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* and we need to route all of our configuration space through it.
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*/
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if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) {
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/*
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* No slots less than 11 on the primary bus on U3 and lower
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*/
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if (slot < 11)
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return (0);
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cfgval = (1 << slot) | (func << 8) | (reg & 0xfc);
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} else {
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cfgval = (bus << 16) | (slot << 11) | (func << 8) |
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(reg & 0xfc) | 1;
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}
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/* Set extended register bits on U4 */
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if (sc->sc_ver == 4)
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cfgval |= (reg >> 8) << 28;
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do {
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out32rb(sc->sc_addr, cfgval);
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} while (in32rb(sc->sc_addr) != cfgval);
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return (1);
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}
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