6fb7bdd343
This is pretty much a complete rewrite based on the existing i386 code. The patches have been circulating for a couple years and have been looked at by plenty of people, but I'm not putting anybody on the hook as having reviewed this in any formal sense except myself. After this has gotten wider testing from the user community, ARM_NEW_PMAP will become the default and various dregs of the old pmap code will be removed. Submitted by: Svatopluk Kraus <onwahe@gmail.com>, Michal Meloun <meloun@miracle.cz>
328 lines
11 KiB
C
328 lines
11 KiB
C
/*-
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* Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
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* Copyright 2014 Michal Meloun <meloun@miracle.cz>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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/*
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* Domain Types for the Domain Access Control Register.
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*/
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#define DOMAIN_FAULT 0x00 /* no access */
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#define DOMAIN_CLIENT 0x01 /* client */
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#define DOMAIN_RESERVED 0x02 /* reserved */
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#define DOMAIN_MANAGER 0x03 /* manager */
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/*
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* TEX remap registers attributes
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*/
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#define PRRR_SO 0 /* Strongly ordered memory */
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#define PRRR_DEV 1 /* Device memory */
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#define PRRR_MEM 2 /* Normal memory */
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#define PRRR_DS0 (1 << 16) /* Shared bit for Device, S = 0 */
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#define PRRR_DS1 (1 << 17) /* Shared bit for Device, S = 1 */
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#define PRRR_NS0 (1 << 18) /* Shared bit for Normal, S = 0 */
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#define PRRR_NS1 (1 << 19) /* Shared bit for Normal, S = 1 */
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#define PRRR_NOS_SHIFT 24 /* base shif for Not Outer Shared bits */
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#define NMRR_NC 0 /* Noncachable*/
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#define NMRR_WB_WA 1 /* Write Back, Write Allocate */
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#define NMRR_WT 2 /* Write Through, Non-Write Allocate */
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#define NMRR_WB 3 /* Write Back, Non-Write Allocate */
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/*
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*
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* The ARM MMU is capable of mapping memory in the following chunks:
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*
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* 16M Supersections (L1 table)
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*
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* 1M Sections (L1 table)
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*
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* 64K Large Pages (L2 table)
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*
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* 4K Small Pages (L2 table)
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*
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*
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* Coarse Tables can map Large and Small Pages.
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* Coarse Tables are 1K in length.
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*
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* The Translation Table Base register holds the pointer to the
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* L1 Table. The L1 Table is a 16K contiguous chunk of memory
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* aligned to a 16K boundary. Each entry in the L1 Table maps
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* 1M of virtual address space, either via a Section mapping or
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* via an L2 Table.
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*
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*/
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#define L1_TABLE_SIZE 0x4000 /* 16K */
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#define L1_ENTRIES 0x1000 /* 4K */
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#define L2_TABLE_SIZE 0x0400 /* 1K */
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#define L2_ENTRIES 0x0100 /* 256 */
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/* ARMv6 super-sections. */
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#define L1_SUP_SIZE 0x01000000 /* 16M */
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#define L1_SUP_OFFSET (L1_SUP_SIZE - 1)
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#define L1_SUP_FRAME (~L1_SUP_OFFSET)
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#define L1_SUP_SHIFT 24
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#define L1_S_SIZE 0x00100000 /* 1M */
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#define L1_S_OFFSET (L1_S_SIZE - 1)
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#define L1_S_FRAME (~L1_S_OFFSET)
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#define L1_S_SHIFT 20
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#define L2_L_SIZE 0x00010000 /* 64K */
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#define L2_L_OFFSET (L2_L_SIZE - 1)
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#define L2_L_FRAME (~L2_L_OFFSET)
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#define L2_L_SHIFT 16
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#define L2_S_SIZE 0x00001000 /* 4K */
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#define L2_S_OFFSET (L2_S_SIZE - 1)
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#define L2_S_FRAME (~L2_S_OFFSET)
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#define L2_S_SHIFT 12
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/*
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* ARM MMU L1 Descriptors
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*/
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#define L1_TYPE_INV 0x00 /* Invalid (fault) */
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#define L1_TYPE_C 0x01 /* Coarse L2 */
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#define L1_TYPE_S 0x02 /* Section */
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#define L1_TYPE_MASK 0x03 /* Mask of type bits */
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/* L1 Section Descriptor */
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#define L1_S_B 0x00000004 /* bufferable Section */
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#define L1_S_C 0x00000008 /* cacheable Section */
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#define L1_S_NX 0x00000010 /* not executeable */
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#define L1_S_DOM(x) ((x) << 5) /* domain */
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#define L1_S_DOM_MASK L1_S_DOM(0xf)
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#define L1_S_P 0x00000200 /* ECC enable for this section */
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#define L1_S_AP(x) ((x) << 10) /* access permissions */
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#define L1_S_AP0 0x00000400 /* access permissions bit 0 */
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#define L1_S_AP1 0x00000800 /* access permissions bit 1 */
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#define L1_S_TEX(x) ((x) << 12) /* type extension */
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#define L1_S_TEX0 0x00001000 /* type extension bit 0 */
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#define L1_S_TEX1 0x00002000 /* type extension bit 1 */
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#define L1_S_TEX2 0x00004000 /* type extension bit 2 */
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#define L1_S_AP2 0x00008000 /* access permissions bit 2 */
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#define L1_S_SHARED 0x00010000 /* shared */
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#define L1_S_NG 0x00020000 /* not global */
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#define L1_S_SUPERSEC 0x00040000 /* Section is a super-section. */
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#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */
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/* L1 Coarse Descriptor */
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#define L1_C_DOM(x) ((x) << 5) /* domain */
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#define L1_C_DOM_MASK L1_C_DOM(0xf)
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#define L1_C_P 0x00000200 /* ECC enable for this section */
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#define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */
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/*
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* ARM MMU L2 Descriptors
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*/
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#define L2_TYPE_INV 0x00 /* Invalid (fault) */
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#define L2_TYPE_L 0x01 /* Large Page - 64k - not used yet*/
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#define L2_TYPE_S 0x02 /* Small Page - 4 */
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#define L2_TYPE_MASK 0x03
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#define L2_NX 0x00000001 /* Not executable */
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#define L2_B 0x00000004 /* Bufferable page */
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#define L2_C 0x00000008 /* Cacheable page */
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#define L2_AP(x) ((x) << 4)
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#define L2_AP0 0x00000010 /* access permissions bit 0*/
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#define L2_AP1 0x00000020 /* access permissions bit 1*/
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#define L2_TEX(x) ((x) << 6) /* type extension */
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#define L2_TEX0 0x00000040 /* type extension bit 0 */
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#define L2_TEX1 0x00000080 /* type extension bit 1 */
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#define L2_TEX2 0x00000100 /* type extension bit 2 */
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#define L2_AP2 0x00000200 /* access permissions bit 2*/
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#define L2_SHARED 0x00000400 /* shared */
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#define L2_NG 0x00000800 /* not global */
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/*
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* TEX classes encoding
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*/
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#define TEX1_CLASS_0 ( 0)
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#define TEX1_CLASS_1 ( L1_S_B)
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#define TEX1_CLASS_2 ( L1_S_C )
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#define TEX1_CLASS_3 ( L1_S_C | L1_S_B)
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#define TEX1_CLASS_4 (L1_S_TEX0 )
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#define TEX1_CLASS_5 (L1_S_TEX0 | L1_S_B)
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#define TEX1_CLASS_6 (L1_S_TEX0 | L1_S_C ) /* Reserved for ARM11 */
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#define TEX1_CLASS_7 (L1_S_TEX0 | L1_S_C | L1_S_B)
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#define TEX2_CLASS_0 ( 0)
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#define TEX2_CLASS_1 ( L2_B)
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#define TEX2_CLASS_2 ( L2_C )
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#define TEX2_CLASS_3 ( L2_C | L2_B)
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#define TEX2_CLASS_4 (L2_TEX0 )
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#define TEX2_CLASS_5 (L2_TEX0 | L2_B)
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#define TEX2_CLASS_6 (L2_TEX0 | L2_C ) /* Reserved for ARM11 */
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#define TEX2_CLASS_7 (L2_TEX0 | L2_C | L2_B)
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/* L1 table definitions. */
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#define NB_IN_PT1 L1_TABLE_SIZE
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#define NPTE1_IN_PT1 L1_ENTRIES
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/* L2 table definitions. */
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#define NB_IN_PT2 L2_TABLE_SIZE
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#define NPTE2_IN_PT2 L2_ENTRIES
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/*
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* Map memory attributes to TEX classes
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*/
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#define PTE2_ATTR_WB_WA TEX2_CLASS_0
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#define PTE2_ATTR_NOCACHE TEX2_CLASS_1
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#define PTE2_ATTR_DEVICE TEX2_CLASS_2
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#define PTE2_ATTR_SO TEX2_CLASS_3
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/*
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* Software defined bits for L1 descriptors
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* - L1_AP0 is used as page accessed bit
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* - L1_AP2 (RO / not RW) is used as page not modified bit
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* - L1_TEX0 is used as software emulated RO bit
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*/
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#define PTE1_V L1_TYPE_S /* Valid bit */
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#define PTE1_A L1_S_AP0 /* Accessed - software emulated */
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#define PTE1_NM L1_S_AP2 /* not modified bit - software emulated
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* used as real write enable bit */
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#define PTE1_M 0 /* Modified (dummy) */
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#define PTE1_S L1_S_SHARED /* Shared */
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#define PTE1_NG L1_S_NG /* Not global */
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#define PTE1_G 0 /* Global (dummy) */
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#define PTE1_NX L1_S_NX /* Not executable */
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#define PTE1_X 0 /* Executable (dummy) */
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#define PTE1_RO L1_S_TEX1 /* Read Only */
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#define PTE1_RW 0 /* Read-Write (dummy) */
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#define PTE1_U L1_S_AP1 /* User */
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#define PTE1_NU 0 /* Not user (kernel only) (dummy) */
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#define PTE1_W L1_S_TEX2 /* Wired */
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#define PTE1_SHIFT L1_S_SHIFT
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#define PTE1_SIZE L1_S_SIZE
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#define PTE1_OFFSET L1_S_OFFSET
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#define PTE1_FRAME L1_S_FRAME
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#define PTE1_ATTR_MASK (L1_S_TEX0 | L1_S_C | L1_S_B)
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#define PTE1_AP_KR (PTE1_RO | PTE1_NM)
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#define PTE1_AP_KRW 0
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#define PTE1_AP_KRUR (PTE1_RO | PTE1_NM | PTE1_U)
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#define PTE1_AP_KRWURW PTE1_U
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/*
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* PTE1 descriptors creation macros.
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*/
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#define PTE1_PA(pa) ((pa) & PTE1_FRAME)
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#define PTE1_AP_COMMON (PTE1_V | PTE1_S)
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#define PTE1(pa, ap, attr) (PTE1_PA(pa) | (ap) | (attr) | PTE1_AP_COMMON)
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#define PTE1_KERN(pa, ap, attr) PTE1(pa, (ap) | PTE1_A | PTE1_G, attr)
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#define PTE1_KERN_NG(pa, ap, attr) PTE1(pa, (ap) | PTE1_A | PTE1_NG, attr)
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#define PTE1_LINK(pa) (((pa) & L1_C_ADDR_MASK) | L1_TYPE_C)
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/*
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* Software defined bits for L2 descriptors
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* - L2_AP0 is used as page accessed bit
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* - L2_AP2 (RO / not RW) is used as page not modified bit
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* - L2_TEX0 is used as software emulated RO bit
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*/
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#define PTE2_V L2_TYPE_S /* Valid bit */
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#define PTE2_A L2_AP0 /* Accessed - software emulated */
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#define PTE2_NM L2_AP2 /* not modified bit - software emulated
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* used as real write enable bit */
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#define PTE2_M 0 /* Modified (dummy) */
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#define PTE2_S L2_SHARED /* Shared */
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#define PTE2_NG L2_NG /* Not global */
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#define PTE2_G 0 /* Global (dummy) */
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#define PTE2_NX L2_NX /* Not executable */
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#define PTE2_X 0 /* Not executable (dummy) */
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#define PTE2_RO L2_TEX1 /* Read Only */
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#define PTE2_U L2_AP1 /* User */
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#define PTE2_NU 0 /* Not user (kernel only) (dummy) */
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#define PTE2_W L2_TEX2 /* Wired */
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#define PTE2_SHIFT L2_S_SHIFT
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#define PTE2_SIZE L2_S_SIZE
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#define PTE2_OFFSET L2_S_OFFSET
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#define PTE2_FRAME L2_S_FRAME
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#define PTE2_ATTR_MASK (L2_TEX0 | L2_C | L2_B)
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#define PTE2_AP_KR (PTE2_RO | PTE2_NM)
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#define PTE2_AP_KRW 0
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#define PTE2_AP_KRUR (PTE2_RO | PTE2_NM | PTE2_U)
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#define PTE2_AP_KRWURW PTE2_U
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/*
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* PTE2 descriptors creation macros.
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*/
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#define PTE2_PA(pa) ((pa) & PTE2_FRAME)
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#define PTE2_AP_COMMON (PTE2_V | PTE2_S)
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#define PTE2(pa, ap, attr) (PTE2_PA(pa) | (ap) | (attr) | PTE2_AP_COMMON)
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#define PTE2_KERN(pa, ap, attr) PTE2(pa, (ap) | PTE2_A | PTE2_G, attr)
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#define PTE2_KERN_NG(pa, ap, attr) PTE2(pa, (ap) | PTE2_A | PTE2_NG, attr)
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// ----------------- TO BE DELETED ---------------------------------------------
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/*
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* sys/arm/arm/elf_trampoline.c
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*/
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#define AP_KRW 0x01 /* kernel read/write */
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/*
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* lib/libkvm/kvm_arm.c
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*/
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#define L1_ADDR_MASK 0xfffffc00
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/*
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* lib/libkvm/kvm_arm.c
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*/
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#define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */
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#ifndef LOCORE
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/*
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* sys/arm/arm/minidump_machdep.c
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* sys/arm/arm/pmap.c
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* sys/arm/arm/pmap.h (hack for our hack in pmap.h )
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* lib/libkvm/kvm_arm.c
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*/
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typedef uint32_t pd_entry_t; /* page directory entry */
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/*
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* sys/arm/arm/minidump_machdep.c
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* sys/arm/arm/pmap.c
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* sys/arm/arm/pmap.h (hack for our hack in pmap.h )
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* sys/arm/include/param.h
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*/
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typedef uint32_t pt_entry_t; /* page table entry */
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#endif
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// -----------------------------------------------------------------------------
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#endif /* !_MACHINE_PTE_H_ */
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