2675d18f77
Reading register $29 with RDHWR is becoming the de-facto standard to implement TLS. According to linux-mips wiki, MIPS Technologies has reserved hardware register $29 for ABI use. Furthermore current GCC makes the following assumptions: - RDHWR is natively available or otherwise emulated by the kernel - Register $29 holds the TLS pointer Submitted by: Robert Millan <rmh@debian.org>
424 lines
9.2 KiB
C
424 lines
9.2 KiB
C
/* $OpenBSD: mips_opcode.h,v 1.2 1999/01/27 04:46:05 imp Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)mips_opcode.h 8.1 (Berkeley) 6/10/93
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* JNPR: mips_opcode.h,v 1.1 2006/08/07 05:38:57 katta
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* $FreeBSD$
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*/
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#ifndef _MACHINE_MIPS_OPCODE_H_
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#define _MACHINE_MIPS_OPCODE_H_
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/*
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* Define the instruction formats and opcode values for the
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* MIPS instruction set.
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*/
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#include <machine/endian.h>
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/*
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* Define the instruction formats.
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*/
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typedef union {
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unsigned word;
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#if BYTE_ORDER == BIG_ENDIAN
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struct {
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unsigned op: 6;
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unsigned rs: 5;
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unsigned rt: 5;
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unsigned imm: 16;
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} IType;
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struct {
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unsigned op: 6;
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unsigned target: 26;
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} JType;
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struct {
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unsigned op: 6;
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unsigned rs: 5;
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unsigned rt: 5;
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unsigned rd: 5;
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unsigned shamt: 5;
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unsigned func: 6;
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} RType;
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struct {
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unsigned op: 6; /* always '0x11' */
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unsigned : 1; /* always '1' */
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unsigned fmt: 4;
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unsigned ft: 5;
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unsigned fs: 5;
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unsigned fd: 5;
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unsigned func: 6;
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} FRType;
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#endif
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#if BYTE_ORDER == LITTLE_ENDIAN
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struct {
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unsigned imm: 16;
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unsigned rt: 5;
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unsigned rs: 5;
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unsigned op: 6;
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} IType;
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struct {
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unsigned target: 26;
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unsigned op: 6;
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} JType;
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struct {
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unsigned func: 6;
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unsigned shamt: 5;
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unsigned rd: 5;
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unsigned rt: 5;
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unsigned rs: 5;
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unsigned op: 6;
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} RType;
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struct {
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unsigned func: 6;
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unsigned fd: 5;
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unsigned fs: 5;
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unsigned ft: 5;
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unsigned fmt: 4;
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unsigned : 1; /* always '1' */
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unsigned op: 6; /* always '0x11' */
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} FRType;
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#endif
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} InstFmt;
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/* instruction field decoding macros */
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#define MIPS_INST_OPCODE(val) (val >> 26)
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#define MIPS_INST_RS(val) ((val & 0x03e00000) >> 21)
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#define MIPS_INST_RT(val) ((val & 0x001f0000) >> 16)
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#define MIPS_INST_IMM(val) ((val & 0x0000ffff))
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#define MIPS_INST_RD(val) ((val & 0x0000f800) >> 11)
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#define MIPS_INST_SA(val) ((val & 0x000007c0) >> 6)
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#define MIPS_INST_FUNC(val) (val & 0x0000003f)
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#define MIPS_INST_INDEX(val) (val & 0x03ffffff)
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/*
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* the mips opcode and function table use a 3bit row and 3bit col
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* number we define the following macro for easy transcribing
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*/
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#define MIPS_OPCODE(r, c) (((r & 0x07) << 3) | (c & 0x07))
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/*
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* Values for the 'op' field.
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*/
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#define OP_SPECIAL 000
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#define OP_BCOND 001
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#define OP_J 002
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#define OP_JAL 003
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#define OP_BEQ 004
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#define OP_BNE 005
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#define OP_BLEZ 006
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#define OP_BGTZ 007
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#define OP_REGIMM OP_BCOND
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#define OP_ADDI 010
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#define OP_ADDIU 011
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#define OP_SLTI 012
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#define OP_SLTIU 013
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#define OP_ANDI 014
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#define OP_ORI 015
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#define OP_XORI 016
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#define OP_LUI 017
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#define OP_COP0 020
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#define OP_COP1 021
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#define OP_COP2 022
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#define OP_COP3 023
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#define OP_BEQL 024
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#define OP_BNEL 025
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#define OP_BLEZL 026
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#define OP_BGTZL 027
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#define OP_COP1X OP_COP3
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#define OP_DADDI 030
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#define OP_DADDIU 031
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#define OP_LDL 032
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#define OP_LDR 033
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#define OP_SPECIAL2 034
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#define OP_JALX 035
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#define OP_SPECIAL3 037
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#define OP_LB 040
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#define OP_LH 041
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#define OP_LWL 042
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#define OP_LW 043
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#define OP_LBU 044
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#define OP_LHU 045
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#define OP_LWR 046
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#define OP_LWU 047
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#define OP_SB 050
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#define OP_SH 051
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#define OP_SWL 052
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#define OP_SW 053
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#define OP_SDL 054
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#define OP_SDR 055
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#define OP_SWR 056
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#define OP_CACHE 057
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#define OP_LL 060
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#define OP_LWC1 061
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#define OP_LWC2 062
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#define OP_LWC3 063
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#define OP_LLD 064
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#define OP_LDC1 065
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#define OP_LDC2 066
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#define OP_LD 067
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#define OP_PREF OP_LWC3
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#define OP_SC 070
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#define OP_SWC1 071
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#define OP_SWC2 072
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#define OP_SWC3 073
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#define OP_SCD 074
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#define OP_SDC1 075
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#define OP_SDC2 076
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#define OP_SD 077
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/*
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* Values for the 'func' field when 'op' == OP_SPECIAL.
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*/
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#define OP_SLL 000
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#define OP_MOVCI 001
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#define OP_SRL 002
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#define OP_SRA 003
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#define OP_SLLV 004
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#define OP_SRLV 006
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#define OP_SRAV 007
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#define OP_F_SLL OP_SLL
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#define OP_F_MOVCI OP_MOVCI
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#define OP_F_SRL OP_SRL
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#define OP_F_SRA OP_SRA
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#define OP_F_SLLV OP_SLLV
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#define OP_F_SRLV OP_SRLV
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#define OP_F_SRAV OP_SRAV
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#define OP_JR 010
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#define OP_JALR 011
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#define OP_MOVZ 012
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#define OP_MOVN 013
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#define OP_SYSCALL 014
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#define OP_BREAK 015
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#define OP_SYNC 017
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#define OP_F_JR OP_JR
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#define OP_F_JALR OP_JALR
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#define OP_F_MOVZ OP_MOVZ
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#define OP_F_MOVN OP_MOVN
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#define OP_F_SYSCALL OP_SYSCALL
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#define OP_F_BREAK OP_BREAK
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#define OP_F_SYNC OP_SYNC
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#define OP_MFHI 020
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#define OP_MTHI 021
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#define OP_MFLO 022
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#define OP_MTLO 023
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#define OP_DSLLV 024
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#define OP_DSRLV 026
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#define OP_DSRAV 027
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#define OP_F_MFHI OP_MFHI
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#define OP_F_MTHI OP_MTHI
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#define OP_F_MFLO OP_MFLO
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#define OP_F_MTLO OP_MTLO
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#define OP_F_DSLLV OP_DSLLV
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#define OP_F_DSRLV OP_DSRLV
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#define OP_F_DSRAV OP_DSRAV
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#define OP_MULT 030
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#define OP_MULTU 031
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#define OP_DIV 032
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#define OP_DIVU 033
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#define OP_DMULT 034
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#define OP_DMULTU 035
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#define OP_DDIV 036
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#define OP_DDIVU 037
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#define OP_F_MULT OP_MULT
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#define OP_F_MULTU OP_MULTU
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#define OP_F_DIV OP_DIV
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#define OP_F_DIVU OP_DIVU
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#define OP_F_DMULT OP_DMULT
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#define OP_F_DMULTU OP_DMULTU
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#define OP_F_DDIV OP_DDIV
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#define OP_F_DDIVU OP_DDIVU
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#define OP_ADD 040
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#define OP_ADDU 041
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#define OP_SUB 042
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#define OP_SUBU 043
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#define OP_AND 044
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#define OP_OR 045
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#define OP_XOR 046
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#define OP_NOR 047
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#define OP_F_ADD OP_ADD
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#define OP_F_ADDU OP_ADDU
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#define OP_F_SUB OP_SUB
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#define OP_F_SUBU OP_SUBU
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#define OP_F_AND OP_AND
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#define OP_F_OR OP_OR
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#define OP_F_XOR OP_XOR
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#define OP_F_NOR OP_NOR
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#define OP_SLT 052
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#define OP_SLTU 053
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#define OP_DADD 054
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#define OP_DADDU 055
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#define OP_DSUB 056
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#define OP_DSUBU 057
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#define OP_F_SLT OP_SLT
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#define OP_F_SLTU OP_SLTU
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#define OP_F_DADD OP_DADD
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#define OP_F_DADDU OP_DADDU
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#define OP_F_DSUB OP_DSUB
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#define OP_F_DSUBU OP_DSUBU
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#define OP_TGE 060
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#define OP_TGEU 061
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#define OP_TLT 062
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#define OP_TLTU 063
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#define OP_TEQ 064
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#define OP_TNE 066
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#define OP_F_TGE OP_TGE
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#define OP_F_TGEU OP_TGEU
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#define OP_F_TLT OP_TLT
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#define OP_F_TLTU OP_TLTU
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#define OP_F_TEQ OP_TEQ
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#define OP_F_TNE OP_TNE
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#define OP_DSLL 070
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#define OP_DSRL 072
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#define OP_DSRA 073
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#define OP_DSLL32 074
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#define OP_DSRL32 076
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#define OP_DSRA32 077
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#define OP_F_DSLL OP_DSLL
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#define OP_F_DSRL OP_DSRL
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#define OP_F_DSRA OP_DSRA
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#define OP_F_DSLL32 OP_DSLL32
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#define OP_F_DSRL32 OP_DSRL32
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#define OP_F_DSRA32 OP_DSRA32
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/*
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* The REGIMM - register immediate instructions are further
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* decoded using this table that has 2bit row numbers, hence
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* a need for a new helper macro.
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*/
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#define MIPS_ROP(r, c) ((r & 0x03) << 3) | (c & 0x07)
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/*
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* Values for the 'func' field when 'op' == OP_BCOND.
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*/
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#define OP_BLTZ 000
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#define OP_BGEZ 001
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#define OP_BLTZL 002
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#define OP_BGEZL 003
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#define OP_R_BLTZ OP_BLTZ
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#define OP_R_BGEZ OP_BGEZ
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#define OP_R_BLTZL OP_BLTZL
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#define OP_R_BGEZL OP_BGEZL
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#define OP_TGEI 010
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#define OP_TGEIU 011
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#define OP_TLTI 012
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#define OP_TLTIU 013
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#define OP_TEQI 014
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#define OP_TNEI 016
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#define OP_R_TGEI OP_TGEI
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#define OP_R_TGEIU OP_TGEIU
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#define OP_R_TLTI OP_TLTI
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#define OP_R_TLTIU OP_TLTIU
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#define OP_R_TEQI OP_TEQI
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#define OP_R_TNEI OP_TNEI
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#define OP_BLTZAL 020
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#define OP_BGEZAL 021
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#define OP_BLTZALL 022
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#define OP_BGEZALL 023
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#define OP_R_BLTZAL OP_BLTZAL
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#define OP_R_BGEZAL OP_BGEZAL
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#define OP_R_BLTZALL OP_BLTZALL
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#define OP_R_BGEZALL OP_BGEZALL
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/*
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* Values for the 'func' field when 'op' == OP_SPECIAL3.
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*/
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#define OP_RDHWR 073
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/*
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* Values for the 'rs' field when 'op' == OP_COPz.
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*/
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#define OP_MF 000
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#define OP_DMF 001
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#define OP_MT 004
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#define OP_DMT 005
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#define OP_BCx 010
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#define OP_BCy 014
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#define OP_CF 002
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#define OP_CT 006
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/*
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* Values for the 'rt' field when 'op' == OP_COPz.
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*/
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#define COPz_BC_TF_MASK 0x01
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#define COPz_BC_TRUE 0x01
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#define COPz_BC_FALSE 0x00
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#define COPz_BCL_TF_MASK 0x02
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#define COPz_BCL_TRUE 0x02
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#define COPz_BCL_FALSE 0x00
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#endif /* !_MACHINE_MIPS_OPCODE_H_ */
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