48af45c161
newer ultras and probably other sun machines. This is a pretty decent chip with 32 byte read and write fifos and support for many higher baud rates. It supports hdlc and sdlc as well as asynchronoue serial, but the goal here is just decent serial console support for the sparc64 port, so these modes are not expected to be supported. So far this only has support for the low level routines used by kernel printf and thus ddb over serial, a character device which can be used for login consoles has not yet been written.
206 lines
8.5 KiB
C
206 lines
8.5 KiB
C
/*-
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* Copyright (c) 2002 Jake Burkholder.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_SE_SEREG_H_
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#define _DEV_SE_SEREG_H_
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#define SE_DIV(n, m) (((m) << 6) | ((n) - 1))
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#define SE_DIV_9600 SE_DIV(48, 2)
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#define SE_DIV_19200 SE_DIV(48, 1)
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#define SE_DIV_38400 SE_DIV(24, 1)
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#define SE_DIV_115200 SE_DIV(8, 1)
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#define SE_CHA 0x0 /* channel a offset */
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#define SE_CHB 0x40 /* channel b offset */
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#define SE_RFIFO 0x0 /* receive fifo */
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#define SE_XFIFO 0x0 /* transmit fifo */
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#define SE_STAR 0x20 /* status register */
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#define STAR_CTS 0x2 /* clear to send state */
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#define STAR_CEC 0x4 /* command executing */
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#define STAR_TEC 0x8 /* tic executing */
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#define STAR_FCS 0x10 /* flow control status */
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#define STAR_RFNE 0x20 /* receive fifo not empty */
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#define STAR_XFW 0x40 /* transmit fifo write enable */
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#define STAR_XDOV 0x80 /* transmit data overflow */
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#define SE_CMDR 0x20 /* command register */
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#define CMDR_XRES 0x1 /* transmitter reset */
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#define CMDR_XF 0x8 /* transmit frame */
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#define CMDR_STI 0x10 /* start timer */
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#define CMDR_RFRD 0x20 /* receive fifo read enable */
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#define CMDR_RRES 0x40 /* reveiver reset */
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#define CMDR_RMC 0x80 /* receive message complete */
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#define SE_MODE 0x22 /* mode register */
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#define MODE_TLP 0x1 /* test loop */
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#define MODE_TRS 0x2 /* timer resolution */
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#define MODE_RTS 0x4 /* request to send */
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#define MODE_RAC 0x8 /* receiver active */
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#define MODE_FLON 0x10 /* flow control on */
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#define MODE_FCTS 0x20 /* flow control using cts */
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#define MODE_FRTS 0x40 /* flow control using rts */
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#define SE_TIMR 0x23 /* timer register */
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#define SE_XON 0x24 /* xon character */
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#define SE_XOFF 0x25 /* xoff character */
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#define SE_TCR 0x26 /* transmit character register */
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#define SE_DAFO 0x27 /* data format */
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#define DAFO_CHL 0x2 /* character length */
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#define DAFO_CHL_8 0x0 /* 8 bits */
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#define DAFO_CHL_7 0x1 /* 7 bits */
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#define DAFO_CHL_6 0x2 /* 6 bits */
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#define DAFO_CHL_5 0x3 /* 5 bits */
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#define DAFO_PARE 0x4 /* parity enable */
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#define DAFO_PAR 0x18 /* parity format */
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#define DAFO_STOP 0x20 /* stop bit */
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#define DAFO_XBRK 0x40 /* transmit break */
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#define SE_RFC 0x28 /* rfifo control register */
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#define RFC_TCDE 0x1 /* termination character detection enable */
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#define RFC_RFTH 0xc /* rfifo threshold level */
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#define RFC_RFTH_2 0x0 /* 2 bytes */
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#define RFC_RFTH_4 0x4 /* 4 bytes */
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#define RFC_RFTH_16 0x8 /* 16 bytes */
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#define RFC_RFTH_32 0xc /* 32 bytes */
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#define RFC_RFDF 0x10 /* rfifo data format */
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#define RFC_DXS 0x20 /* disable storage of xon/xoff characters */
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#define RFC_DPS 0x40 /* disable parity storage */
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#define SE_RBCL 0x2a /* receive byte count low */
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#define SE_XBCL 0x2a /* transmit byte count low */
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#define SE_RBCH 0x2b /* receive byte count high */
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#define SE_XBCH 0x2b /* transmit byte count high */
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#define SE_CCR0 0x2c /* channel configuration register 0 */
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#define CCR0_SM 0x3 /* serial mode */
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#define CCR0_SM_HDLC 0x0 /* hdlc/sdlc mode */
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#define CCR0_SM_SDLC 0x1 /* sdlc loop mode */
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#define CCR0_SM_BISYNC 0x2 /* bisync mode */
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#define CCR0_SM_ASYNC 0x3 /* async mode */
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#define CCR0_SC 0x1c /* serial configuration */
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#define CCR0_SC_NRZ 0x0 /* nrz data encoding */
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#define CCR0_SC_NRZI 0x2 /* nrzi data encoding */
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#define CCR0_SC_FM0 0x4 /* fm0 data encoding */
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#define CCR0_SC_FM1 0x5 /* fm1 data encoding */
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#define CCR0_SC_MCHSTR 0x6 /* manchester data encoding */
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#define CCR0_MCE 0x40 /* master clock enable */
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#define CCR0_PU 0x80 /* power up */
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#define SE_CCR1 0x2d /* channel configuration register 1 */
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#define CCR1_CM 0x7 /* clock mode */
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#define CCR1_CM_7 0x7 /* clock mode 7 */
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#define CCR1_BCR 0x8 /* bit clock rate */
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#define CCR1_ODS 0x10 /* output driver select */
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#define SE_CCR2 0x2e /* channel configuration register 2 */
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#define CCR2_DIV 0x1 /* data inversion */
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#define CCR2_RWX 0x4 /* read/write exchange */
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#define CCR2_TOE 0x8 /* txclk ouput enable */
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#define CCR2_SSEL 0x10 /* clock source select */
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#define CCR2_BDF 0x20 /* baud rate division factor */
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#define CCR2_BR8 0x40 /* baud rate 8 */
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#define CCR2_BR9 0x80 /* baud rate 9 */
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#define CCR2_RCS0 0x10 /* receive clock shift 0 (5) */
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#define CCR2_XCS0 0x20 /* transmit clock shift 0 (5) */
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#define CCR2_SOC0 0x40 /* special output control 0 (0a, 1, 4, 5) */
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#define CCR2_SOC1 0x80 /* special output control 1 (0a, 1, 4, 5) */
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#define SE_CCR3 0x2f /* channel configuration register 3 */
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#define CCR3_PSD 0x1 /* dpll phase shift disable */
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#define SE_TSAX 0x30 /* transmit timeslot assignment register */
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#define SE_TSAR 0x31 /* receive timeslot assignment register */
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#define SE_XCCR 0x32 /* transmit channel capacity register */
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#define SE_RCCR 0x33 /* receive channel capacity register */
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#define SE_VSTR 0x34 /* version status register */
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#define VSTR_VN 0xf /* version number 0 */
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#define VSTR_DPLA 0x40 /* dpll asynchronous */
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#define VSTR_CD 0x80 /* carrier detect */
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#define SE_BGR 0x34 /* baud rate generator register */
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#define SE_TIC 0x35 /* trasmit immediate character */
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#define SE_MXN 0x36 /* mask xon character */
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#define SE_MXF 0x37 /* mask xoff character */
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#define SE_GIS 0x38 /* global interrupt status */
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#define GIS_ISB0 0x1 /* interrupt status channel B 0 */
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#define GIS_ISB1 0x2 /* interrupt status channel B 1 */
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#define GIS_ISA0 0x4 /* interrupt status channel A 0 */
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#define GIS_ISA1 0x8 /* interrupt status channel A 1 */
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#define GIS_PI 0x80 /* univerisal port interrupt */
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#define SE_IVA 0x38 /* interrupt vector address */
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#define SE_IPC 0x39 /* interrupt port configuration */
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#define IPC_IC0 0x1 /* interrupt configuration 0 */
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#define IPC_IC1 0x2 /* interrupt configuration 1 */
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#define IPC_CASM 0x4 /* cascading mode */
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#define IPC_SLA0 0x8 /* slave address 0 */
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#define IPC_SLA1 0x10 /* slave address 1 */
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#define IPC_VIS 0x80 /* masked interrupts visible */
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#define SE_ISR0 0x3a /* interrupt status 0 */
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#define ISR0_RPF 0x1 /* receive pool full */
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#define ISR0_RFO 0x2 /* receive frame overflow */
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#define ISR0_CDSC 0x4 /* carrier detect status change */
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#define ISR0_PLLA 0x8 /* dpll asynchronous */
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#define ISR0_FERR 0x10 /* framing error */
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#define ISR0_PERR 0x20 /* parity error */
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#define ISR0_TIME 0x40 /* time out */
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#define ISR0_TCD 0x80 /* termination character detected */
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#define SE_IMR0 0x3a /* interrupt mask 0 */
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#define SE_ISR1 0x3b /* interrupt status 1 */
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#define ISR1_XPR 0x1 /* transmit pool ready */
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#define ISR1_XON 0x2 /* transmit message repeat */
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#define ISR1_CSC 0x4 /* clear to send status change */
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#define ISR1_TIN 0x8 /* timer interrupt */
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#define ISR1_XOFF 0x10 /* xoff character detected */
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#define ISR1_ALLS 0x20 /* all sent */
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#define ISR1_BRKT 0x40 /* break terminated */
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#define ISR1_BRK 0x80 /* break */
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#define SE_IMR1 0x3b /* interrupt mask 1 */
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#define SE_PVR 0x3c /* port value register */
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#define SE_PIS 0x3d /* port interrupt status */
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#define SE_PIM 0x3d /* port interrupt mask */
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#define SE_PCR 0x3e /* port configuration register */
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#define SE_CCR4 0x3f /* channel configuration register 4 */
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#define CCR4_ICD 0x10 /* invert polarity of carrier detect signal */
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#define CCR4_TST1 0x20 /* test pin */
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#define CCR4_EBRG 0x40 /* enhanced baud rate generator mode */
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#define CCR4_MCK4 0x80 /* master clock divide by 4 */
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#endif
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