96efd46222
drivers into the revived sys/sparc64/pci/ofw_pci.c, previously already serving a similar purpose. This has been done with sun4v in mind, which explains a) the otherwise not that obvious scheme employed and b) why reusing sys/powerpc/ofw/ofw_pci.c was even lesser an option. - Add a workaround for QEMU once again not emulating real machines, in this case by not providing the OFW_PCI_CS_MEM64 range. [1] Submitted by: jhb [1] MFC after: 1 week
358 lines
16 KiB
C
358 lines
16 KiB
C
/*-
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* Copyright (c) 2002 Jason L. Wright (jason@thought.net)
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* Copyright (c) 2005 by Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULLAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* from: OpenBSD: schizoreg.h,v 1.8 2005/05/19 18:28:59 mickey Exp
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* $FreeBSD$
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*/
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#ifndef _SPARC64_PCI_SCHIZOREG_H_
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#define _SPARC64_PCI_SCHIZOREG_H_
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#define STX_NINTR 5 /* 4 via OFW + 1 CDMA */
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#define SCZ_NREG 3
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#define TOM_NREG 4
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#define STX_PCI 0
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#define STX_CTRL 1
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#define STX_PCICFG 2
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#define STX_ICON 3
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/* PCI configuration and status registers */
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#define SX_PCI_CFG_ICD 0x00110
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#define STX_PCI_IOMMU 0x00200
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#define STX_PCI_IOMMU_CTXFLUSH 0x00218
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#define STX_PCI_IMAP_BASE 0x01000
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#define STX_PCI_ICLR_BASE 0x01400
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#define STX_PCI_INTR_RETRY_TIM 0x01a00
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#define SCZ_PCI_DMA_SYNC 0x01a08
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#define TOM_PCI_DMA_SYNC_COMP 0x01a10
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#define TOMXMS_PCI_DMA_SYNC_PEND 0x01a18
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#define STX_PCI_CTRL 0x02000
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#define STX_PCI_AFSR 0x02010
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#define STX_PCI_AFAR 0x02018
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#define STX_PCI_DIAG 0x02020
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#define XMS_PCI_PARITY_DETECT 0x02040
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#define TOM_PCI_IOC_CSR 0x02248
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#define TOM_PCI_IOC_TAG 0x02290
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#define TOM_PCI_IOC_DATA 0x02290
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#define XMS_PCI_X_ERR_STAT 0x02300
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#define XMS_PCI_X_DIAG 0x02308
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#define XMS_PCI_UPPER_RETRY_COUNTER 0x02310
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#define STX_PCI_STRBUF 0x02800
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#define STX_PCI_STRBUF_CTXFLUSH 0x02818
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#define STX_PCI_IOMMU_SVADIAG 0x0a400
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#define STX_PCI_IOMMU_TLB_CMP_DIAG 0x0a408
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#define STX_PCI_IOMMU_QUEUE_DIAG 0x0a500
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#define STX_PCI_IOMMU_TLB_TAG_DIAG 0x0a580
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#define STX_PCI_IOMMU_TLB_DATA_DIAG 0x0a600
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#define STX_PCI_IOBIO_DIAG 0x0a808
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#define STX_PCI_STRBUF_CTXMATCH 0x10000
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/* PCI configuration/idle check diagnostic register */
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#define SX_PCI_CFG_ICD_PCI_2_0_COMPAT 0x0000000000008000ULL
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#define SX_PCI_CFG_ICD_DMAW_PERR_IEN 0x0000000000004000ULL
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#define SX_PCI_CFG_ICD_IFC_NOT_IDLE 0x0000000000000010ULL
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#define SX_PCI_CFG_ICD_MDU_NOT_IDLE 0x0000000000000008ULL
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#define SX_PCI_CFG_ICD_MMU_NOT_IDLE 0x0000000000000004ULL
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#define SX_PCI_CFG_ICD_PBM_NOT_IDLE 0x0000000000000002ULL
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#define SX_PCI_CFG_ICD_STC_NOT_IDLE 0x0000000000000001ULL
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/* PCI IOMMU control register */
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#define TOM_PCI_IOMMU_ERR_BAD_VA 0x0000000010000000ULL
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#define TOM_PCI_IOMMU_ERR_ILLTSBTBW 0x0000000008000000ULL
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#define TOM_PCI_IOMMU_ECC_ERR 0x0000000006000000ULL
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#define TOM_PCI_IOMMU_TIMEOUT_ERR 0x0000000004000000ULL
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#define TOM_PCI_IOMMU_INVALID_ERR 0x0000000002000000ULL
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#define TOM_PCI_IOMMU_PROTECTION_ERR 0x0000000000000000ULL
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#define TOM_PCI_IOMMU_ERRMASK \
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(TOM_PCI_IOMMU_PROTECTION_ERR | TOM_PCI_IOMMU_INVALID_ERR | \
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TOM_PCI_IOMMU_TIMEOUT_ERR | TOM_PCI_IOMMU_ECC_ERR)
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#define TOM_PCI_IOMMU_ERR 0x0000000001000000ULL
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/* PCI control/status register */
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#define SCZ_PCI_CTRL_BUS_UNUS 0x8000000000000000ULL
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#define TOM_PCI_CTRL_DTO_ERR 0x4000000000000000ULL
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#define TOM_PCI_CTRL_DTO_IEN 0x2000000000000000ULL
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#define SCZ_PCI_CTRL_ESLCK 0x0008000000000000ULL
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#define XMS_PCI_CTRL_DMA_WR_PERR 0x0008000000000000ULL
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#define SCZ_PCI_CTRL_ERRSLOT 0x0007000000000000ULL
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#define STX_PCI_CTRL_TTO_ERR 0x0000004000000000ULL
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#define STX_PCI_CTRL_RTRY_ERR 0x0000002000000000ULL
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#define STX_PCI_CTRL_MMU_ERR 0x0000001000000000ULL
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#define SCZ_PCI_CTRL_SBH_ERR 0x0000000800000000ULL
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#define STX_PCI_CTRL_SERR 0x0000000400000000ULL
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#define SCZ_PCI_CTRL_PCISPD 0x0000000200000000ULL
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#define XMS_PCI_CTRL_X_MODE 0x0000000100000000ULL
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#define TOM_PCI_CTRL_PRM 0x0000000040000000ULL
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#define TOM_PCI_CTRL_PRO 0x0000000020000000ULL
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#define TOM_PCI_CTRL_PRL 0x0000000010000000ULL
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#define STX_PCI_CTRL_PTO 0x0000000003000000ULL
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#define XMS_PCI_CTRL_X_ERRINT_EN 0x0000000000100000ULL
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#define STX_PCI_CTRL_MMU_IEN 0x0000000000080000ULL
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#define STX_PCI_CTRL_SBH_IEN 0x0000000000040000ULL
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#define STX_PCI_CTRL_ERR_IEN 0x0000000000020000ULL
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#define STX_PCI_CTRL_ARB_PARK 0x0000000000010000ULL
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#define SCZ_PCI_CTRL_PCIRST 0x0000000000000100ULL
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#define STX_PCI_CTRL_ARB_MASK 0x00000000000000ffULL
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#define XMS_PCI_CTRL_XMITS10_ARB_MASK 0x000000000000000fULL
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/* PCI asynchronous fault status register */
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#define STX_PCI_AFSR_P_MA 0x8000000000000000ULL
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#define STX_PCI_AFSR_P_TA 0x4000000000000000ULL
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#define STX_PCI_AFSR_P_RTRY 0x2000000000000000ULL
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#define STX_PCI_AFSR_P_PERR 0x1000000000000000ULL
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#define STX_PCI_AFSR_P_TTO 0x0800000000000000ULL
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#define STX_PCI_AFSR_P_UNUS 0x0400000000000000ULL
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#define STX_PCI_AFSR_S_MA 0x0200000000000000ULL
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#define STX_PCI_AFSR_S_TA 0x0100000000000000ULL
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#define STX_PCI_AFSR_S_RTRY 0x0080000000000000ULL
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#define STX_PCI_AFSR_S_PERR 0x0040000000000000ULL
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#define STX_PCI_AFSR_S_TTO 0x0020000000000000ULL
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#define STX_PCI_AFSR_S_UNUS 0x0010000000000000ULL
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#define STX_PCI_AFSR_DWMASK 0x0000030000000000ULL
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#define STX_PCI_AFSR_BMASK 0x000000ff00000000ULL
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#define STX_PCI_AFSR_BLK 0x0000000080000000ULL
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#define STX_PCI_AFSR_CFG 0x0000000040000000ULL
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#define STX_PCI_AFSR_MEM 0x0000000020000000ULL
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#define STX_PCI_AFSR_IO 0x0000000010000000ULL
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/* PCI diagnostic register */
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#define SCZ_PCI_DIAG_BADECC_DIS 0x0000000000000400ULL
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#define STX_PCI_DIAG_BYPASS_DIS 0x0000000000000200ULL
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#define STX_PCI_DIAG_TTO_DIS 0x0000000000000100ULL
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#define SCZ_PCI_DIAG_RTRYARB_DIS 0x0000000000000080ULL
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#define STX_PCI_DIAG_RETRY_DIS 0x0000000000000040ULL
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#define STX_PCI_DIAG_INTRSYNC_DIS 0x0000000000000020ULL
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#define STX_PCI_DIAG_DMAPARITY_INV 0x0000000000000008ULL
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#define STX_PCI_DIAG_PIODPARITY_INV 0x0000000000000004ULL
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#define STX_PCI_DIAG_PIOAPARITY_INV 0x0000000000000002ULL
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/* Tomatillo I/O cache register */
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#define TOM_PCI_IOC_PW 0x0000000000080000ULL
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#define TOM_PCI_IOC_PRM 0x0000000000040000ULL
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#define TOM_PCI_IOC_PRO 0x0000000000020000ULL
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#define TOM_PCI_IOC_PRL 0x0000000000010000ULL
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#define TOM_PCI_IOC_PRM_LEN 0x000000000000c000ULL
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#define TOM_PCI_IOC_PRM_LEN_SHIFT 14
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#define TOM_PCI_IOC_PRO_LEN 0x0000000000003000ULL
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#define TOM_PCI_IOC_PRO_LEN_SHIFT 12
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#define TOM_PCI_IOC_PRL_LEN 0x0000000000000c00ULL
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#define TOM_PCI_IOC_PRL_LEN_SHIFT 10
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#define TOM_PCI_IOC_PREF_OFF 0x0000000000000038ULL
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#define TOM_PCI_IOC_PREF_OFF_SHIFT 3
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#define TOM_PCI_IOC_CPRM 0x0000000000000004ULL
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#define TOM_PCI_IOC_CPRO 0x0000000000000002ULL
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#define TOM_PCI_IOC_CPRL 0x0000000000000001ULL
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/* XMITS PCI-X error status register */
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#define XMS_PCI_X_ERR_STAT_P_SC_DSCRD 0x8000000000000000ULL
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#define XMS_PCI_X_ERR_STAT_P_SC_TTO 0x4000000000000000ULL
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#define XMS_PCI_X_ERR_STAT_P_SDSTAT 0x2000000000000000ULL
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#define XMS_PCI_X_ERR_STAT_P_SMMU 0x1000000000000000ULL
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#define XMS_PCI_X_ERR_STAT_P_CDSTAT 0x0800000000000000ULL
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#define XMS_PCI_X_ERR_STAT_P_CMMU 0x0400000000000000ULL
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#define XMS_PCI_X_ERR_STAT_S_SC_DSCRD 0x0080000000000000ULL
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#define XMS_PCI_X_ERR_STAT_S_SC_TTO 0x0040000000000000ULL
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#define XMS_PCI_X_ERR_STAT_S_SDSTAT 0x0020000000000000ULL
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#define XMS_PCI_X_ERR_STAT_S_SMMU 0x0010000000000000ULL
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#define XMS_PCI_X_ERR_STAT_S_CDSTAT 0x0008000000000000ULL
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#define XMS_PCI_X_ERR_STAT_S_CMMU 0x0004000000000000ULL
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#define XMS_PCI_X_ERR_STAT_PERR_RCV_IEN 0x0000000400000000ULL
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#define XMS_PCI_X_ERR_STAT_PERR_RCV 0x0000000200000000ULL
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#define XMS_PCI_X_ERR_STAT_SERR_ON_PERR 0x0000000100000000ULL
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/* XMITS PCI-X diagnostic register */
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#define XMS_PCI_X_DIAG_DIS_FAIR 0x0000000000080000ULL
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#define XMS_PCI_X_DIAG_CRCQ_VALID 0x0000000000040000ULL
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#define XMS_PCI_X_DIAG_SRCQ_ONE 0x0000000000000200ULL
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#define XMS_PCI_X_DIAG_CRCQ_FLUSH 0x0000000000000100ULL
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#define XMS_PCI_X_DIAG_BUGCNTL_MASK 0x0000ffff00000000ULL
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#define XMS_PCI_X_DIAG_BUGCNTL_SHIFT 32
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#define XMS_PCI_X_DIAG_SRCQ_MASK 0x00000000000000ffULL
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/* Controller configuration and status registers */
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/* Note that these are shared on Schizo but per-PBM on Tomatillo. */
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#define STX_CTRL_BUS_ERRLOG 0x00018
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#define STX_CTRL_ECCCTRL 0x00020
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#define STX_CTRL_UE_AFSR 0x00030
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#define STX_CTRL_UE_AFAR 0x00038
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#define STX_CTRL_CE_AFSR 0x00040
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#define STX_CTRL_CE_AFAR 0x00048
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#define STX_CTRL_PERF 0x07000
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#define STX_CTRL_PERF_CNT 0x07008
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/* Safari/JBus error log register */
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#define STX_CTRL_BUS_ERRLOG_BADCMD 0x4000000000000000ULL
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#define SCZ_CTRL_BUS_ERRLOG_SSMDIS 0x2000000000000000ULL
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#define SCZ_CTRL_BUS_ERRLOG_BADMA 0x1000000000000000ULL
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#define SCZ_CTRL_BUS_ERRLOG_BADMB 0x0800000000000000ULL
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#define SCZ_CTRL_BUS_ERRLOG_BADMC 0x0400000000000000ULL
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#define TOM_CTRL_BUS_ERRLOG_SNOOP_GR 0x0000000000200000ULL
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#define TOM_CTRL_BUS_ERRLOG_SNOOP_PCI 0x0000000000100000ULL
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#define TOM_CTRL_BUS_ERRLOG_SNOOP_RD 0x0000000000080000ULL
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#define TOM_CTRL_BUS_ERRLOG_SNOOP_RDS 0x0000000000020000ULL
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#define TOM_CTRL_BUS_ERRLOG_SNOOP_RDSA 0x0000000000010000ULL
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#define TOM_CTRL_BUS_ERRLOG_SNOOP_OWN 0x0000000000008000ULL
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#define TOM_CTRL_BUS_ERRLOG_SNOOP_RDO 0x0000000000004000ULL
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#define SCZ_CTRL_BUS_ERRLOG_CPU1PS 0x0000000000002000ULL
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#define TOM_CTRL_BUS_ERRLOG_WDATA_PERR 0x0000000000002000ULL
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#define SCZ_CTRL_BUS_ERRLOG_CPU1PB 0x0000000000001000ULL
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#define TOM_CTRL_BUS_ERRLOG_CTRL_PERR 0x0000000000001000ULL
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#define SCZ_CTRL_BUS_ERRLOG_CPU0PS 0x0000000000000800ULL
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#define TOM_CTRL_BUS_ERRLOG_SNOOP_ERR 0x0000000000000800ULL
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#define SCZ_CTRL_BUS_ERRLOG_CPU0PB 0x0000000000000400ULL
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#define TOM_CTRL_BUS_ERRLOG_JBUS_ILL_B 0x0000000000000400ULL
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#define SCZ_CTRL_BUS_ERRLOG_CIQTO 0x0000000000000200ULL
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#define SCZ_CTRL_BUS_ERRLOG_LPQTO 0x0000000000000100ULL
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#define TOM_CTRL_BUS_ERRLOG_JBUS_ILL_C 0x0000000000000100ULL
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#define SCZ_CTRL_BUS_ERRLOG_SFPQTO 0x0000000000000080ULL
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#define SCZ_CTRL_BUS_ERRLOG_UFPQTO 0x0000000000000040ULL
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#define TOM_CTRL_BUS_ERRLOG_RD_PERR 0x0000000000000040ULL
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#define STX_CTRL_BUS_ERRLOG_APERR 0x0000000000000020ULL
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#define STX_CTRL_BUS_ERRLOG_UNMAP 0x0000000000000010ULL
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#define STX_CTRL_BUS_ERRLOG_BUSERR 0x0000000000000004ULL
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#define STX_CTRL_BUS_ERRLOG_TIMEOUT 0x0000000000000002ULL
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#define SCZ_CTRL_BUS_ERRLOG_ILL 0x0000000000000001ULL
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/* ECC control register */
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#define STX_CTRL_ECCCTRL_EE 0x8000000000000000ULL
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#define STX_CTRL_ECCCTRL_UE 0x4000000000000000ULL
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#define STX_CTRL_ECCCTRL_CE 0x2000000000000000ULL
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/* Uncorrectable error asynchronous fault status register */
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#define STX_CTRL_UE_AFSR_P_PIO 0x8000000000000000ULL
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#define STX_CTRL_UE_AFSR_P_DRD 0x4000000000000000ULL
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#define STX_CTRL_UE_AFSR_P_DWR 0x2000000000000000ULL
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#define STX_CTRL_UE_AFSR_S_PIO 0x1000000000000000ULL
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#define STX_CTRL_UE_AFSR_S_DRD 0x0800000000000000ULL
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#define STX_CTRL_UE_AFSR_S_DWR 0x0400000000000000ULL
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#define STX_CTRL_UE_AFSR_ERRPNDG 0x0300000000000000ULL
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#define STX_CTRL_UE_AFSR_BMASK 0x000003ff00000000ULL
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#define STX_CTRL_UE_AFSR_QOFF 0x00000000c0000000ULL
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#define STX_CTRL_UE_AFSR_AID 0x000000001f000000ULL
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#define STX_CTRL_UE_AFSR_PARTIAL 0x0000000000800000ULL
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#define STX_CTRL_UE_AFSR_OWNEDIN 0x0000000000400000ULL
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#define STX_CTRL_UE_AFSR_MTAGSYND 0x00000000000f0000ULL
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#define STX_CTRL_UE_AFSR_MTAG 0x000000000000e000ULL
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#define STX_CTRL_UE_AFSR_ECCSYND 0x00000000000001ffULL
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/* Correctable error asynchronous fault status register */
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#define STX_CTRL_CE_AFSR_P_PIO 0x8000000000000000ULL
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#define STX_CTRL_CE_AFSR_P_DRD 0x4000000000000000ULL
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#define STX_CTRL_CE_AFSR_P_DWR 0x2000000000000000ULL
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#define STX_CTRL_CE_AFSR_S_PIO 0x1000000000000000ULL
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#define STX_CTRL_CE_AFSR_S_DRD 0x0800000000000000ULL
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#define STX_CTRL_CE_AFSR_S_DWR 0x0400000000000000ULL
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#define STX_CTRL_CE_AFSR_ERRPNDG 0x0300000000000000ULL
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#define STX_CTRL_CE_AFSR_BMASK 0x000003ff00000000ULL
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#define STX_CTRL_CE_AFSR_QOFF 0x00000000c0000000ULL
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#define STX_CTRL_CE_AFSR_AID 0x000000001f000000ULL
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#define STX_CTRL_CE_AFSR_PARTIAL 0x0000000000800000ULL
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#define STX_CTRL_CE_AFSR_OWNEDIN 0x0000000000400000ULL
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#define STX_CTRL_CE_AFSR_MTAGSYND 0x00000000000f0000ULL
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#define STX_CTRL_CE_AFSR_MTAG 0x000000000000e000ULL
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#define STX_CTRL_CE_AFSR_ECCSYND 0x00000000000001ffULL
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/*
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* Safari/JBus performance control register
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* NB: For Tomatillo only events 0x00 through 0x08 are documented as
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* implemented.
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*/
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#define SCZ_CTRL_PERF_ZDATA_OUT 0x0000000000000016ULL
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#define SCZ_CTRL_PERF_ZDATA_IN 0x0000000000000015ULL
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#define SCZ_CTRL_PERF_ORQFULL 0x0000000000000014ULL
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#define SCZ_CTRL_PERF_DVMA_WR 0x0000000000000013ULL
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#define SCZ_CTRL_PERF_DVMA_RD 0x0000000000000012ULL
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#define SCZ_CTRL_PERF_CYCPSESYS 0x0000000000000011ULL
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#define STX_CTRL_PERF_PCI_B 0x000000000000000fULL
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#define STX_CTRL_PERF_PCI_A 0x000000000000000eULL
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#define STX_CTRL_PERF_UPA 0x000000000000000dULL
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#define STX_CTRL_PERF_PIOINTRNL 0x000000000000000cULL
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#define TOM_CTRL_PERF_WRI_WRIS 0x000000000000000bULL
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#define STX_CTRL_PERF_INTRS 0x000000000000000aULL
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#define STX_CTRL_PERF_PRTLWRMRGBUF 0x0000000000000009ULL
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#define STX_CTRL_PERF_FGN_IO_HITS 0x0000000000000008ULL
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#define STX_CTRL_PERF_FGN_IO_TRNS 0x0000000000000007ULL
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#define STX_CTRL_PERF_OWN_CHRNT_HITS 0x0000000000000006ULL
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#define STX_CTRL_PERF_OWN_CHRNT_TRNS 0x0000000000000005ULL
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#define SCZ_CTRL_PERF_FGN_CHRNT_HITS 0x0000000000000004ULL
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#define STX_CTRL_PERF_FGN_CHRNT_TRNS 0x0000000000000003ULL
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#define STX_CTRL_PERF_CYCLES_PAUSE 0x0000000000000002ULL
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#define STX_CTRL_PERF_BUSCYC 0x0000000000000001ULL
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#define STX_CTRL_PERF_DIS 0x0000000000000000ULL
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#define STX_CTRL_PERF_CNT1_SHIFT 11
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#define STX_CTRL_PERF_CNT0_SHIFT 4
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/* Safari/JBus performance counter register */
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#define STX_CTRL_PERF_CNT_MASK 0x00000000ffffffffULL
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#define STX_CTRL_PERF_CNT_CNT1_SHIFT 32
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#define STX_CTRL_PERF_CNT_CNT0_SHIFT 0
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/* INO defines */
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#define STX_FB0_INO 0x2a /* FB0 int. shared w/ UPA64s */
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#define STX_FB1_INO 0x2b /* FB1 int. shared w/ UPA64s */
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#define STX_UE_INO 0x30 /* uncorrectable error */
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#define STX_CE_INO 0x31 /* correctable error */
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#define STX_PCIERR_A_INO 0x32 /* PCI bus A error */
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#define STX_PCIERR_B_INO 0x33 /* PCI bus B error */
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#define STX_BUS_INO 0x34 /* Safari/JBus error */
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#define STX_CDMA_A_INO 0x35 /* PCI bus A CDMA */
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#define STX_CDMA_B_INO 0x36 /* PCI bus B CDMA */
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#define STX_MAX_INO 0x37
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/* Device space defines */
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#define STX_CONF_SIZE 0x1000000
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#define STX_CONF_BUS_SHIFT 16
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#define STX_CONF_DEV_SHIFT 11
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#define STX_CONF_FUNC_SHIFT 8
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#define STX_CONF_REG_SHIFT 0
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#define STX_IO_SIZE 0x1000000
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#define STX_MEM_SIZE 0x100000000
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#define STX_CONF_OFF(bus, slot, func, reg) \
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(((bus) << STX_CONF_BUS_SHIFT) | \
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((slot) << STX_CONF_DEV_SHIFT) | \
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((func) << STX_CONF_FUNC_SHIFT) | \
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((reg) << STX_CONF_REG_SHIFT))
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/* Definitions for the Schizo/Tomatillo configuration space */
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#define STX_CS_DEVICE 0 /* bridge CS device number */
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#define STX_CS_FUNC 0 /* brdige CS function number */
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/* Non-Standard registers in the configration space */
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/*
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* NB: For Tomatillo the secondary and subordinate bus number registers
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* apparently are read-only although documented otherwise; writing to
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* them just triggers a PCI bus error interrupt or has no effect at best.
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*/
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#define STX_CSR_SECBUS 0x40 /* secondary bus number */
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#define STX_CSR_SUBBUS 0x41 /* subordinate bus number */
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/* Width of the physical addresses the IOMMU translates to */
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#define STX_IOMMU_BITS 43
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#endif /* !_SPARC64_PCI_SCHIZOREG_H_ */
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