083cb45b1a
FDT attachment to a new file. A separate ACPI attachment will then be added to allow arm64 servers with ACPI to use it over FDT. This should also help with merging this with the ofwpci driver, with further work needed to remove restrictions this driver places on resource allocation. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D7319
160 lines
4.5 KiB
C
160 lines
4.5 KiB
C
/*-
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* Copyright (c) 2015,2016 Annapurna Labs Ltd. and affiliates
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Alpine PCI/PCI-Express controller driver.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/intr.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/pci/pci_host_generic.h>
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#include <dev/pci/pci_host_generic_fdt.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include "pcib_if.h"
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#include "contrib/alpine-hal/al_hal_unit_adapter_regs.h"
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#include "contrib/alpine-hal/al_hal_pcie.h"
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#include "contrib/alpine-hal/al_hal_pcie_axi_reg.h"
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#define ANNAPURNA_VENDOR_ID 0x1c36
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/* Forward prototypes */
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static int al_pcib_probe(device_t);
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static int al_pcib_attach(device_t);
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static void al_pcib_fixup(device_t);
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static struct ofw_compat_data compat_data[] = {
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{"annapurna-labs,al-internal-pcie", true},
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{"annapurna-labs,alpine-internal-pcie", true},
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{NULL, false}
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};
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/*
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* Bus interface definitions.
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*/
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static device_method_t al_pcib_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, al_pcib_probe),
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DEVMETHOD(device_attach, al_pcib_attach),
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DEVMETHOD_END
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};
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DEFINE_CLASS_1(pcib, al_pcib_driver, al_pcib_methods,
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sizeof(struct generic_pcie_fdt_softc), generic_pcie_fdt_driver);
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static devclass_t anpa_pcib_devclass;
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DRIVER_MODULE(alpine_pcib, simplebus, al_pcib_driver, anpa_pcib_devclass, 0, 0);
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DRIVER_MODULE(alpine_pcib, ofwbus, al_pcib_driver, anpa_pcib_devclass, 0, 0);
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static int
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al_pcib_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
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return (ENXIO);
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device_set_desc(dev,
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"Annapurna-Labs Integrated Internal PCI-E Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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al_pcib_attach(device_t dev)
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{
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int rv;
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rv = pci_host_generic_attach(dev);
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/* Annapurna quirk: configure vendor-specific registers */
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if (rv == 0)
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al_pcib_fixup(dev);
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return (rv);
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}
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static void
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al_pcib_fixup(device_t dev)
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{
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uint32_t val;
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uint16_t vid;
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uint8_t hdrtype;
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int bus, slot, func, maxfunc;
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/* Fixup is only needed on bus 0 */
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bus = 0;
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for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
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maxfunc = 0;
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for (func = 0; func <= maxfunc; func++) {
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hdrtype = PCIB_READ_CONFIG(dev, bus, slot, func,
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PCIR_HDRTYPE, 1);
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if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
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continue;
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if (func == 0 && (hdrtype & PCIM_MFDEV) != 0)
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maxfunc = PCI_FUNCMAX;
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vid = PCIB_READ_CONFIG(dev, bus, slot, func,
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PCIR_VENDOR, 2);
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if (vid == ANNAPURNA_VENDOR_ID) {
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val = PCIB_READ_CONFIG(dev, bus, slot, func,
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AL_PCI_AXI_CFG_AND_CTR_0, 4);
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val |= PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_MASK;
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PCIB_WRITE_CONFIG(dev, bus, slot, func,
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AL_PCI_AXI_CFG_AND_CTR_0, val, 4);
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val = PCIB_READ_CONFIG(dev, bus, slot, func,
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AL_PCI_APP_CONTROL, 4);
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val &= ~0xffff;
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val |= PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_TGTID_MASK;
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PCIB_WRITE_CONFIG(dev, bus, slot, func,
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AL_PCI_APP_CONTROL, val, 4);
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}
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}
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}
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}
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