48f4c9fb04
Some U-Boot versions do not initialize MT7620's Frame Engine. Then it is not possible to receive packets from the network. Setting GDMA1 Frames Destination Port to Port 0 (CPU) in GDM Forwarding Configuration register solves this issue. Submitted by: Hiroki Mori (yamori813@yahoo.co.jp) Reviewed by: adrian mizhka (previous version) Differential Revision: https://reviews.freebsd.org/D9301
347 lines
11 KiB
C
347 lines
11 KiB
C
/*-
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* Copyright (c) 2009, Aleksandr Rybalko
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _IF_RTREG_H_
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#define _IF_RTREG_H_
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#define RT_READ(sc, reg) \
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bus_space_read_4((sc)->bst, (sc)->bsh, reg)
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#define RT_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->bst, (sc)->bsh, reg, val)
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#define GE_PORT_BASE 0x0000
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#define MDIO_ACCESS 0x00
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#define MDIO_CMD_ONGO (1<<31)
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#define MDIO_CMD_WR (1<<30)
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#define MDIO_PHY_ADDR_MASK 0x1f000000
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#define MDIO_PHY_ADDR_SHIFT 24
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#define MDIO_PHYREG_ADDR_MASK 0x001f0000
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#define MDIO_PHYREG_ADDR_SHIFT 16
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#define MDIO_PHY_DATA_MASK 0x0000ffff
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#define MDIO_PHY_DATA_SHIFT 0
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#define FE_GLO_CFG 0x08 /*Frame Engine Global Configuration */
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#define EXT_VLAN_TYPE_MASK 0xffff0000
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#define EXT_VLAN_TYPE_SHIFT 16
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#define EXT_VLAN_TYPE_DFLT 0x81000000
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#define US_CYC_CNT_MASK 0x0000ff00
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#define US_CYC_CNT_SHIFT 8
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#define US_CYC_CNT_DFLT (132<<8) /* sys clocks per 1uS */
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#define L2_SPACE (8<<4) /* L2 space. Unit is 8 bytes */
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#define FE_RST_GLO 0x0C /*Frame Engine Global Reset*/
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#define FC_DROP_CNT_MASK 0xffff0000 /*Flow cntrl drop count */
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#define FC_DROP_CNT_SHIFT 16
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#define PSE_RESET (1<<0)
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/* RT305x interrupt registers */
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#define FE_INT_STATUS 0x10
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#define CNT_PPE_AF (1<<31)
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#define CNT_GDM_AF (1<<29)
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#define PSE_P2_FC (1<<26)
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#define GDM_CRC_DROP (1<<25)
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#define PSE_BUF_DROP (1<<24)
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#define GDM_OTHER_DROP (1<<23)
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#define PSE_P1_FC (1<<22)
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#define PSE_P0_FC (1<<21)
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#define PSE_FQ_EMPTY (1<<20)
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#define INT_TX_COHERENT (1<<17)
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#define INT_RX_COHERENT (1<<16)
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#define INT_TXQ3_DONE (1<<11)
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#define INT_TXQ2_DONE (1<<10)
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#define INT_TXQ1_DONE (1<<9)
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#define INT_TXQ0_DONE (1<<8)
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#define INT_RX_DONE (1<<2)
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#define TX_DLY_INT (1<<1) /* TXQ[0|1]_DONE with delay */
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#define RX_DLY_INT (1<<0) /* RX_DONE with delay */
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#define FE_INT_ENABLE 0x14
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/* RT5350 interrupt registers */
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#define RT5350_FE_INT_STATUS (RT5350_PDMA_BASE + 0x220)
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#define RT5350_INT_RX_COHERENT (1<<31)
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#define RT5350_RX_DLY_INT (1<<30)
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#define RT5350_INT_TX_COHERENT (1<<29)
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#define RT5350_TX_DLY_INT (1<<28)
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#define RT5350_INT_RXQ1_DONE (1<<17)
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#define RT5350_INT_RXQ0_DONE (1<<16)
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#define RT5350_INT_TXQ3_DONE (1<<3)
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#define RT5350_INT_TXQ2_DONE (1<<2)
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#define RT5350_INT_TXQ1_DONE (1<<1)
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#define RT5350_INT_TXQ0_DONE (1<<0)
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#define RT5350_FE_INT_ENABLE (RT5350_PDMA_BASE + 0x228)
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#define MDIO_CFG2 0x18
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#define FOE_TS_T 0x1c
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#define PSE_FQ_PCNT_MASK 0xff000000
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#define PSE_FQ_PCNT_SHIFT 24
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#define FOE_TS_TIMESTAMP_MASK 0x0000ffff
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#define FOE_TS_TIMESTAMP_SHIFT 0
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#define GDMA1_BASE 0x0020
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#define GDMA2_BASE 0x0060
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#define CDMA_BASE 0x0080
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#define MT7620_GDMA1_BASE 0x600
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#define GDMA_FWD_CFG 0x00 /* Only GDMA */
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#define GDM_DROP_256B (1<<23)
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#define GDM_ICS_EN (1<<22)
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#define GDM_TCS_EN (1<<21)
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#define GDM_UCS_EN (1<<20)
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#define GDM_DISPAD (1<<18)
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#define GDM_DISCRC (1<<17)
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#define GDM_STRPCRC (1<<16)
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#define GDM_UFRC_P_SHIFT 12
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#define GDM_BFRC_P_SHIFT 8
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#define GDM_MFRC_P_SHIFT 4
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#define GDM_OFRC_P_SHIFT 0
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#define GDM_XFRC_P_MASK 0x07
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#define GDM_DST_PORT_CPU 0
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#define GDM_DST_PORT_GDMA1 1
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#define GDM_DST_PORT_GDMA2 2
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#define GDM_DST_PORT_PPE 6
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#define GDM_DST_PORT_DISCARD 7
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#define CDMA_CSG_CFG 0x00 /* Only CDMA */
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#define INS_VLAN_TAG (0x8100<<16)
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#define ICS_GEN_EN (1<<2)
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#define TCS_GEN_EN (1<<1)
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#define UCS_GEN_EN (1<<0)
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#define GDMA_SCH_CFG 0x04
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#define GDM1_SCH_MOD_MASK 0x03000000
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#define GDM1_SCH_MOD_SHIFT 24
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#define GDM1_SCH_MOD_WRR 0
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#define GDM1_SCH_MOD_STRICT 1
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#define GDM1_SCH_MOD_MIXED 2
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#define GDM1_WT_1 0
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#define GDM1_WT_2 1
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#define GDM1_WT_4 2
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#define GDM1_WT_8 3
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#define GDM1_WT_16 4
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#define GDM1_WT_Q3_SHIFT 12
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#define GDM1_WT_Q2_SHIFT 8
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#define GDM1_WT_Q1_SHIFT 4
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#define GDM1_WT_Q0_SHIFT 0
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#define GDMA_SHPR_CFG 0x08
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#define GDM1_SHPR_EN (1<<24)
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#define GDM1_BK_SIZE_MASK 0x00ff0000 /* Bucket size 1kB units */
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#define GDM1_BK_SIZE_SHIFT 16
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#define GDM1_TK_RATE_MASK 0x00003fff /* Shaper token rate 8B/ms units */
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#define GDM1_TK_RATE_SHIFT 0
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#define GDMA_MAC_ADRL 0x0C
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#define GDMA_MAC_ADRH 0x10
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#define PPPOE_SID_0001 0x08 /* 0..15 SID0, 15..31 SID1 */
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#define PPPOE_SID_0203 0x0c
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#define PPPOE_SID_0405 0x10
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#define PPPOE_SID_0607 0x14
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#define PPPOE_SID_0809 0x18
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#define PPPOE_SID_1011 0x1c
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#define PPPOE_SID_1213 0x20
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#define PPPOE_SID_1415 0x24
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#define VLAN_ID_0001 0x28 /* 0..11 VID0, 15..26 VID1 */
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#define VLAN_ID_0203 0x2c
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#define VLAN_ID_0405 0x30
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#define VLAN_ID_0607 0x34
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#define VLAN_ID_0809 0x38
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#define VLAN_ID_1011 0x3c
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#define VLAN_ID_1213 0x40
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#define VLAN_ID_1415 0x44
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#define PSE_BASE 0x0040
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#define PSE_FQFC_CFG 0x00
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#define FQ_MAX_PCNT_MASK 0xff000000
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#define FQ_MAX_PCNT_SHIFT 24
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#define FQ_FC_RLS_MASK 0x00ff0000
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#define FQ_FC_RLS_SHIFT 16
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#define FQ_FC_ASRT_MASK 0x0000ff00
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#define FQ_FC_ASRT_SHIFT 8
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#define FQ_FC_DROP_MASK 0x000000ff
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#define FQ_FC_DROP_SHIFT 0
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#define CDMA_FC_CFG 0x04
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#define GDMA1_FC_CFG 0x08
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#define GDMA2_FC_CFG 0x0C
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#define P_SHARING (1<<28)
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#define P_HQ_DEF_MASK 0x0f000000
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#define P_HQ_DEF_SHIFT 24
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#define P_HQ_RESV_MASK 0x00ff0000
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#define P_HQ_RESV_SHIFT 16
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#define P_LQ_RESV_MASK 0x0000ff00
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#define P_LQ_RESV_SHIFT 8
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#define P_IQ_ASRT_MASK 0x000000ff
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#define P_IQ_ASRT_SHIFT 0
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#define CDMA_OQ_STA 0x10
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#define GDMA1_OQ_STA 0x14
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#define GDMA2_OQ_STA 0x18
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#define P_OQ3_PCNT_MASK 0xff000000
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#define P_OQ3_PCNT_SHIFT 24
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#define P_OQ2_PCNT_MASK 0x00ff0000
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#define P_OQ2_PCNT_SHIFT 16
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#define P_OQ1_PCNT_MASK 0x0000ff00
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#define P_OQ1_PCNT_SHIFT 8
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#define P_OQ0_PCNT_MASK 0x000000ff
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#define P_OQ0_PCNT_SHIFT 0
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#define PSE_IQ_STA 0x1C
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#define P6_OQ0_PCNT_MASK 0xff000000
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#define P6_OQ0_PCNT_SHIFT 24
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#define P2_IQ_PCNT_MASK 0x00ff0000
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#define P2_IQ_PCNT_SHIFT 16
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#define P1_IQ_PCNT_MASK 0x0000ff00
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#define P1_IQ_PCNT_SHIFT 8
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#define P0_IQ_PCNT_MASK 0x000000ff
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#define P0_IQ_PCNT_SHIFT 0
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#define PDMA_BASE 0x0100
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#define RT5350_PDMA_BASE 0x0800
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#define PDMA_GLO_CFG 0x00
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#define RT5350_PDMA_GLO_CFG 0x204
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#define FE_TX_WB_DDONE (1<<6)
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#define FE_DMA_BT_SIZE4 (0<<4)
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#define FE_DMA_BT_SIZE8 (1<<4)
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#define FE_DMA_BT_SIZE16 (2<<4)
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#define FE_RX_DMA_BUSY (1<<3)
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#define FE_RX_DMA_EN (1<<2)
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#define FE_TX_DMA_BUSY (1<<1)
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#define FE_TX_DMA_EN (1<<0)
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#define PDMA_RST_IDX 0x04
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#define RT5350_PDMA_RST_IDX 0x208
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#define FE_RST_DRX_IDX0 (1<<16)
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#define FE_RST_DTX_IDX3 (1<<3)
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#define FE_RST_DTX_IDX2 (1<<2)
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#define FE_RST_DTX_IDX1 (1<<1)
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#define FE_RST_DTX_IDX0 (1<<0)
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#define PDMA_SCH_CFG 0x08
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#define RT5350_PDMA_SCH_CFG 0x280
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#define DELAY_INT_CFG 0x0C
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#define RT5350_DELAY_INT_CFG 0x20C
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#define TXDLY_INT_EN (1<<31)
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#define TXMAX_PINT_SHIFT 24
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#define TXMAX_PTIME_SHIFT 16
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#define RXDLY_INT_EN (1<<15)
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#define RXMAX_PINT_SHIFT 8
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#define RXMAX_PTIME_SHIFT 0
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#define TX_BASE_PTR0 0x10
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#define TX_MAX_CNT0 0x14
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#define TX_CTX_IDX0 0x18
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#define TX_DTX_IDX0 0x1C
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#define TX_BASE_PTR1 0x20
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#define TX_MAX_CNT1 0x24
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#define TX_CTX_IDX1 0x28
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#define TX_DTX_IDX1 0x2C
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#define RX_BASE_PTR0 0x30
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#define RX_MAX_CNT0 0x34
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#define RX_CALC_IDX0 0x38
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#define RX_DRX_IDX0 0x3C
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#define TX_BASE_PTR2 0x40
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#define TX_MAX_CNT2 0x44
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#define TX_CTX_IDX2 0x48
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#define TX_DTX_IDX2 0x4C
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#define TX_BASE_PTR3 0x50
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#define TX_MAX_CNT3 0x54
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#define TX_CTX_IDX3 0x58
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#define TX_DTX_IDX3 0x5C
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#define TX_BASE_PTR(qid) (((qid>1)?(0x20):(0x10)) + (qid) * 16)
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#define TX_MAX_CNT(qid) (((qid>1)?(0x24):(0x14)) + (qid) * 16)
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#define TX_CTX_IDX(qid) (((qid>1)?(0x28):(0x18)) + (qid) * 16)
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#define TX_DTX_IDX(qid) (((qid>1)?(0x2c):(0x1c)) + (qid) * 16)
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#define RT5350_TX_BASE_PTR0 0x000
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#define RT5350_TX_MAX_CNT0 0x004
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#define RT5350_TX_CTX_IDX0 0x008
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#define RT5350_TX_DTX_IDX0 0x00C
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#define RT5350_TX_BASE_PTR1 0x010
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#define RT5350_TX_MAX_CNT1 0x014
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#define RT5350_TX_CTX_IDX1 0x018
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#define RT5350_TX_DTX_IDX1 0x01C
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#define RT5350_TX_BASE_PTR2 0x020
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#define RT5350_TX_MAX_CNT2 0x024
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#define RT5350_TX_CTX_IDX2 0x028
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#define RT5350_TX_DTX_IDX2 0x02C
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#define RT5350_TX_BASE_PTR3 0x030
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#define RT5350_TX_MAX_CNT3 0x034
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#define RT5350_TX_CTX_IDX3 0x038
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#define RT5350_TX_DTX_IDX3 0x03C
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#define RT5350_RX_BASE_PTR0 0x100
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#define RT5350_RX_MAX_CNT0 0x104
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#define RT5350_RX_CALC_IDX0 0x108
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#define RT5350_RX_DRX_IDX0 0x10C
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#define RT5350_RX_BASE_PTR1 0x110
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#define RT5350_RX_MAX_CNT1 0x114
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#define RT5350_RX_CALC_IDX1 0x118
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#define RT5350_RX_DRX_IDX1 0x11C
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#define RT5350_TX_BASE_PTR(qid) ((qid) * 0x10 + 0x000)
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#define RT5350_TX_MAX_CNT(qid) ((qid) * 0x10 + 0x004)
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#define RT5350_TX_CTX_IDX(qid) ((qid) * 0x10 + 0x008)
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#define RT5350_TX_DTX_IDX(qid) ((qid) * 0x10 + 0x00C)
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#define PPE_BASE 0x0200
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#define CNTR_BASE 0x0400
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#define PPE_AC_BCNT0 0x000
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#define PPE_AC_PCNT0 0x004
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#define PPE_AC_BCNT63 0x1F8
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#define PPE_AC_PCNT63 0x1FC
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#define PPE_MTR_CNT0 0x200
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#define PPE_MTR_CNT63 0x2FC
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#define GDMA_TX_GBCNT0 0x300
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#define GDMA_TX_GPCNT0 0x304
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#define GDMA_TX_SKIPCNT0 0x308
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#define GDMA_TX_COLCNT0 0x30C
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#define GDMA_RX_GBCNT0 0x320
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#define GDMA_RX_GPCNT0 0x324
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#define GDMA_RX_OERCNT0 0x328
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#define GDMA_RX_FERCNT0 0x32C
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#define GDMA_RX_SHORT_ERCNT0 0x330
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#define GDMA_RX_LONG_ERCNT0 0x334
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#define GDMA_RX_CSUM_ERCNT0 0x338
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#define POLICYTABLE_BASE 0x1000
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#endif /* _IF_RTREG_H_ */
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