e4c8a13d61
to a guest physical address. PG_PS (page size) field is valid only in a PDE or a PDPTE so it is now checked only in non-terminal paging entries. Ignore the upper 32-bits of the CR3 for PAE paging.
144 lines
4.5 KiB
C
144 lines
4.5 KiB
C
/*-
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* Copyright (c) 2012 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _VMM_INSTRUCTION_EMUL_H_
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#define _VMM_INSTRUCTION_EMUL_H_
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enum vie_cpu_mode {
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CPU_MODE_COMPATIBILITY, /* IA-32E mode (CS.L = 0) */
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CPU_MODE_64BIT, /* IA-32E mode (CS.L = 1) */
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};
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enum vie_paging_mode {
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PAGING_MODE_FLAT,
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PAGING_MODE_32,
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PAGING_MODE_PAE,
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PAGING_MODE_64,
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};
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/*
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* The data structures 'vie' and 'vie_op' are meant to be opaque to the
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* consumers of instruction decoding. The only reason why their contents
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* need to be exposed is because they are part of the 'vm_exit' structure.
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*/
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struct vie_op {
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uint8_t op_byte; /* actual opcode byte */
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uint8_t op_type; /* type of operation (e.g. MOV) */
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uint16_t op_flags;
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};
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#define VIE_INST_SIZE 15
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struct vie {
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uint8_t inst[VIE_INST_SIZE]; /* instruction bytes */
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uint8_t num_valid; /* size of the instruction */
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uint8_t num_processed;
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uint8_t rex_w:1, /* REX prefix */
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rex_r:1,
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rex_x:1,
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rex_b:1,
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rex_present:1;
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uint8_t mod:2, /* ModRM byte */
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reg:4,
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rm:4;
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uint8_t ss:2, /* SIB byte */
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index:4,
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base:4;
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uint8_t disp_bytes;
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uint8_t imm_bytes;
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uint8_t scale;
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int base_register; /* VM_REG_GUEST_xyz */
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int index_register; /* VM_REG_GUEST_xyz */
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int64_t displacement; /* optional addr displacement */
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int64_t immediate; /* optional immediate operand */
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uint8_t decoded; /* set to 1 if successfully decoded */
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struct vie_op op; /* opcode description */
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};
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/*
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* Callback functions to read and write memory regions.
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*/
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typedef int (*mem_region_read_t)(void *vm, int cpuid, uint64_t gpa,
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uint64_t *rval, int rsize, void *arg);
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typedef int (*mem_region_write_t)(void *vm, int cpuid, uint64_t gpa,
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uint64_t wval, int wsize, void *arg);
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/*
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* Emulate the decoded 'vie' instruction.
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*
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* The callbacks 'mrr' and 'mrw' emulate reads and writes to the memory region
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* containing 'gpa'. 'mrarg' is an opaque argument that is passed into the
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* callback functions.
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*
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* 'void *vm' should be 'struct vm *' when called from kernel context and
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* 'struct vmctx *' when called from user context.
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* s
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*/
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int vmm_emulate_instruction(void *vm, int cpuid, uint64_t gpa, struct vie *vie,
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mem_region_read_t mrr, mem_region_write_t mrw,
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void *mrarg);
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#ifdef _KERNEL
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/*
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* APIs to fetch and decode the instruction from nested page fault handler.
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*
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* 'vie' must be initialized before calling 'vmm_fetch_instruction()'
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*/
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int vmm_fetch_instruction(struct vm *vm, int cpuid,
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uint64_t rip, int inst_length, uint64_t cr3,
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enum vie_paging_mode paging_mode, int cpl,
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struct vie *vie);
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void vie_init(struct vie *vie);
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/*
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* Decode the instruction fetched into 'vie' so it can be emulated.
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*
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* 'gla' is the guest linear address provided by the hardware assist
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* that caused the nested page table fault. It is used to verify that
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* the software instruction decoding is in agreement with the hardware.
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*
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* Some hardware assists do not provide the 'gla' to the hypervisor.
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* To skip the 'gla' verification for this or any other reason pass
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* in VIE_INVALID_GLA instead.
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*/
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#define VIE_INVALID_GLA (1UL << 63) /* a non-canonical address */
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int vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla,
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enum vie_cpu_mode cpu_mode, struct vie *vie);
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#endif /* _KERNEL */
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#endif /* _VMM_INSTRUCTION_EMUL_H_ */
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