325 lines
9.1 KiB
C
325 lines
9.1 KiB
C
/*-
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* Copyright (c) 2014 Ian Lepore
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Pin mux and pad control driver for imx5 and imx6.
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*
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* This driver implements the fdt_pinctrl interface for configuring the gpio and
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* peripheral pins based on fdt configuration data.
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*
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* When the driver attaches, it walks the entire fdt tree and automatically
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* configures the pins for each device which has a pinctrl-0 property and whose
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* status is "okay". In addition it implements the fdt_pinctrl_configure()
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* method which any other driver can call at any time to reconfigure its pins.
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*
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* The nature of the fsl,pins property in fdt data makes this driver's job very
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* easy. Instead of representing each pin and pad configuration using symbolic
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* properties such as pullup-enable="true" and so on, the data simply contains
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* the addresses of the registers that control the pins, and the raw values to
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* store in those registers.
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*
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* The imx5 and imx6 SoCs also have a small number of "general purpose
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* registers" in the iomuxc device which are used to control an assortment
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* of completely unrelated aspects of SoC behavior. This driver provides other
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* drivers with direct access to those registers via simple accessor functions.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/fdt/fdt_pinctrl.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/freescale/imx/imx_iomuxvar.h>
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#include <arm/freescale/imx/imx_machdep.h>
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struct iomux_softc {
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device_t dev;
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struct resource *mem_res;
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u_int last_gpreg;
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};
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static struct iomux_softc *iomux_sc;
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static struct ofw_compat_data compat_data[] = {
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{"fsl,imx6dl-iomuxc", true},
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{"fsl,imx6q-iomuxc", true},
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{"fsl,imx6sl-iomuxc", true},
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{"fsl,imx6sx-iomuxc", true},
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{"fsl,imx53-iomuxc", true},
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{"fsl,imx51-iomuxc", true},
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{NULL, false},
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};
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/*
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* Each tuple in an fsl,pins property contains these fields.
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*/
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struct pincfg {
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uint32_t mux_reg;
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uint32_t padconf_reg;
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uint32_t input_reg;
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uint32_t mux_val;
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uint32_t input_val;
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uint32_t padconf_val;
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};
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#define PADCONF_NONE (1U << 31) /* Do not configure pad. */
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#define PADCONF_SION (1U << 30) /* Force SION bit in mux register. */
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#define PADMUX_SION (1U << 4) /* The SION bit in the mux register. */
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static inline uint32_t
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RD4(struct iomux_softc *sc, bus_size_t off)
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{
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return (bus_read_4(sc->mem_res, off));
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}
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static inline void
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WR4(struct iomux_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_write_4(sc->mem_res, off, val);
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}
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static void
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iomux_configure_input(struct iomux_softc *sc, uint32_t reg, uint32_t val)
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{
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u_int select, mask, shift, width;
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/* If register and value are zero, there is nothing to configure. */
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if (reg == 0 && val == 0)
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return;
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/*
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* If the config value has 0xff in the high byte it is encoded:
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* 31 23 15 7 0
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* | 0xff | shift | width | select |
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* We need to mask out the old select value and OR in the new, using a
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* mask of the given width and shifting the values up by shift.
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*/
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if ((val & 0xff000000) == 0xff000000) {
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select = val & 0x000000ff;
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width = (val & 0x0000ff00) >> 8;
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shift = (val & 0x00ff0000) >> 16;
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mask = ((1u << width) - 1) << shift;
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val = (RD4(sc, reg) & ~mask) | (select << shift);
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}
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WR4(sc, reg, val);
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}
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static int
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iomux_configure_pins(device_t dev, phandle_t cfgxref)
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{
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struct iomux_softc *sc;
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struct pincfg *cfgtuples, *cfg;
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phandle_t cfgnode;
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int i, ntuples;
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uint32_t sion;
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sc = device_get_softc(dev);
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cfgnode = OF_node_from_xref(cfgxref);
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ntuples = OF_getencprop_alloc(cfgnode, "fsl,pins", sizeof(*cfgtuples),
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(void **)&cfgtuples);
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if (ntuples < 0)
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return (ENOENT);
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if (ntuples == 0)
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return (0); /* Empty property is not an error. */
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for (i = 0, cfg = cfgtuples; i < ntuples; i++, cfg++) {
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sion = (cfg->padconf_val & PADCONF_SION) ? PADMUX_SION : 0;
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WR4(sc, cfg->mux_reg, cfg->mux_val | sion);
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iomux_configure_input(sc, cfg->input_reg, cfg->input_val);
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if ((cfg->padconf_val & PADCONF_NONE) == 0)
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WR4(sc, cfg->padconf_reg, cfg->padconf_val);
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if (bootverbose) {
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char name[32];
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OF_getprop(cfgnode, "name", &name, sizeof(name));
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printf("%16s: muxreg 0x%04x muxval 0x%02x "
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"inpreg 0x%04x inpval 0x%02x "
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"padreg 0x%04x padval 0x%08x\n",
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name, cfg->mux_reg, cfg->mux_val | sion,
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cfg->input_reg, cfg->input_val,
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cfg->padconf_reg, cfg->padconf_val);
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}
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}
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free(cfgtuples, M_OFWPROP);
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return (0);
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}
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static int
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iomux_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
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return (ENXIO);
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device_set_desc(dev, "Freescale i.MX pin configuration");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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iomux_detach(device_t dev)
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{
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/* This device is always present. */
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return (EBUSY);
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}
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static int
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iomux_attach(device_t dev)
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{
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struct iomux_softc * sc;
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int rid;
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sc = device_get_softc(dev);
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sc->dev = dev;
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switch (imx_soc_type()) {
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case IMXSOC_51:
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sc->last_gpreg = 1;
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break;
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case IMXSOC_53:
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sc->last_gpreg = 2;
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break;
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case IMXSOC_6DL:
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case IMXSOC_6S:
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case IMXSOC_6SL:
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case IMXSOC_6Q:
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sc->last_gpreg = 13;
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break;
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default:
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device_printf(dev, "Unknown SoC type\n");
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return (ENXIO);
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}
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "Cannot allocate memory resources\n");
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return (ENXIO);
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}
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iomux_sc = sc;
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/*
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* Register as a pinctrl device, and call the convenience function that
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* walks the entire device tree invoking FDT_PINCTRL_CONFIGURE() on any
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* pinctrl-0 property cells whose xref phandle refers to a configuration
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* that is a child node of our node in the tree.
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*
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* The pinctrl bindings documentation specifically mentions that the
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* pinctrl device itself may have a pinctrl-0 property which contains
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* static configuration to be applied at device init time. The tree
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* walk will automatically handle this for us when it passes through our
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* node in the tree.
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*/
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fdt_pinctrl_register(dev, "fsl,pins");
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fdt_pinctrl_configure_tree(dev);
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return (0);
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}
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uint32_t
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imx_iomux_gpr_get(u_int regnum)
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{
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struct iomux_softc * sc;
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sc = iomux_sc;
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KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__));
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KASSERT(regnum >= 0 && regnum <= sc->last_gpreg,
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("%s bad regnum %u, max %u", __FUNCTION__, regnum, sc->last_gpreg));
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return (RD4(iomux_sc, regnum * 4));
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}
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void
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imx_iomux_gpr_set(u_int regnum, uint32_t val)
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{
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struct iomux_softc * sc;
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sc = iomux_sc;
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KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__));
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KASSERT(regnum >= 0 && regnum <= sc->last_gpreg,
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("%s bad regnum %u, max %u", __FUNCTION__, regnum, sc->last_gpreg));
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WR4(iomux_sc, regnum * 4, val);
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}
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void
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imx_iomux_gpr_set_masked(u_int regnum, uint32_t clrbits, uint32_t setbits)
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{
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struct iomux_softc * sc;
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uint32_t val;
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sc = iomux_sc;
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KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__));
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KASSERT(regnum >= 0 && regnum <= sc->last_gpreg,
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("%s bad regnum %u, max %u", __FUNCTION__, regnum, sc->last_gpreg));
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val = RD4(iomux_sc, regnum * 4);
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val = (val & ~clrbits) | setbits;
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WR4(iomux_sc, regnum * 4, val);
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}
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static device_method_t imx_iomux_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, iomux_probe),
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DEVMETHOD(device_attach, iomux_attach),
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DEVMETHOD(device_detach, iomux_detach),
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/* fdt_pinctrl interface */
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DEVMETHOD(fdt_pinctrl_configure,iomux_configure_pins),
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DEVMETHOD_END
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};
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static driver_t imx_iomux_driver = {
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"imx_iomux",
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imx_iomux_methods,
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sizeof(struct iomux_softc),
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};
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static devclass_t imx_iomux_devclass;
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EARLY_DRIVER_MODULE(imx_iomux, simplebus, imx_iomux_driver,
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imx_iomux_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_LATE);
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