2edabad8a4
* Support for sam9 "EMAC" controller. * Support for rmii interface to phy. at91.c & at91sam9.c: * Eliminate separate at91sam9.c file. * Add new devices to at91sam9_devs table. at91_machdep.c & at at91sam9_machdep.c: * Automatic chip type determination. * Remove compile time chip dependencies. * Eliminate separate at91sam9_machdep.c file. at91_pmc.c: * Corrected support for all of the sam926? and sam9g20 chips. * Remove compile time chip dependencies. My apologies to Greg for taking so long to take care of it.
400 lines
9.6 KiB
C
400 lines
9.6 KiB
C
/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <arm/at91/at91_twireg.h>
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#include <arm/at91/at91var.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include "iicbus_if.h"
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#define TWI_SLOW_CLOCK 1500
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#define TWI_FAST_CLOCK 45000
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#define TWI_FASTEST_CLOCK 90000
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struct at91_twi_softc
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{
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device_t dev; /* Myself */
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void *intrhand; /* Interrupt handle */
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struct resource *irq_res; /* IRQ resource */
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struct resource *mem_res; /* Memory resource */
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struct mtx sc_mtx; /* basically a perimeter lock */
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volatile uint32_t flags;
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uint32_t cwgr;
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int sc_started;
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int twi_addr;
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device_t iicbus;
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};
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static inline uint32_t
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RD4(struct at91_twi_softc *sc, bus_size_t off)
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{
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return bus_read_4(sc->mem_res, off);
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}
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static inline void
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WR4(struct at91_twi_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_write_4(sc->mem_res, off, val);
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}
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#define AT91_TWI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define AT91_TWI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define AT91_TWI_LOCK_INIT(_sc) \
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mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
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"twi", MTX_DEF)
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#define AT91_TWI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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#define AT91_TWI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
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#define AT91_TWI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
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#define TWI_DEF_CLK 100000
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static devclass_t at91_twi_devclass;
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/* bus entry points */
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static int at91_twi_probe(device_t dev);
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static int at91_twi_attach(device_t dev);
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static int at91_twi_detach(device_t dev);
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static void at91_twi_intr(void *);
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/* helper routines */
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static int at91_twi_activate(device_t dev);
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static void at91_twi_deactivate(device_t dev);
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static int
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at91_twi_probe(device_t dev)
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{
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device_set_desc(dev, "TWI");
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return (0);
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}
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static int
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at91_twi_attach(device_t dev)
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{
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struct at91_twi_softc *sc = device_get_softc(dev);
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int err;
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sc->dev = dev;
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err = at91_twi_activate(dev);
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if (err)
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goto out;
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AT91_TWI_LOCK_INIT(sc);
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/*
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* Activate the interrupt
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*/
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err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, at91_twi_intr, sc, &sc->intrhand);
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if (err) {
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AT91_TWI_LOCK_DESTROY(sc);
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goto out;
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}
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sc->cwgr = TWI_CWGR_CKDIV(8 * at91_master_clock / TWI_FASTEST_CLOCK) |
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TWI_CWGR_CHDIV(TWI_CWGR_DIV(TWI_DEF_CLK)) |
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TWI_CWGR_CLDIV(TWI_CWGR_DIV(TWI_DEF_CLK));
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WR4(sc, TWI_CR, TWI_CR_SWRST);
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WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
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WR4(sc, TWI_CWGR, sc->cwgr);
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if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL)
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device_printf(dev, "could not allocate iicbus instance\n");
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/* probe and attach the iicbus */
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bus_generic_attach(dev);
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out:;
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if (err)
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at91_twi_deactivate(dev);
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return (err);
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}
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static int
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at91_twi_detach(device_t dev)
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{
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struct at91_twi_softc *sc;
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int rv;
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sc = device_get_softc(dev);
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at91_twi_deactivate(dev);
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if (sc->iicbus && (rv = device_delete_child(dev, sc->iicbus)) != 0)
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return (rv);
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AT91_TWI_LOCK_DESTROY(sc);
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return (0);
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}
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static int
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at91_twi_activate(device_t dev)
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{
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struct at91_twi_softc *sc;
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int rid;
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sc = device_get_softc(dev);
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL)
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goto errout;
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rid = 0;
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (sc->irq_res == NULL)
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goto errout;
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return (0);
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errout:
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at91_twi_deactivate(dev);
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return (ENOMEM);
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}
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static void
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at91_twi_deactivate(device_t dev)
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{
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struct at91_twi_softc *sc;
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sc = device_get_softc(dev);
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if (sc->intrhand)
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bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
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sc->intrhand = 0;
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bus_generic_detach(sc->dev);
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if (sc->mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY,
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rman_get_rid(sc->mem_res), sc->mem_res);
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sc->mem_res = 0;
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if (sc->irq_res)
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bus_release_resource(dev, SYS_RES_IRQ,
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rman_get_rid(sc->irq_res), sc->irq_res);
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sc->irq_res = 0;
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return;
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}
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static void
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at91_twi_intr(void *xsc)
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{
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struct at91_twi_softc *sc = xsc;
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uint32_t status;
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status = RD4(sc, TWI_SR);
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if (status == 0)
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return;
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AT91_TWI_LOCK(sc);
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sc->flags |= status & (TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_NACK);
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if (status & TWI_SR_RXRDY)
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sc->flags |= TWI_SR_RXRDY;
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if (status & TWI_SR_TXRDY)
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sc->flags |= TWI_SR_TXRDY;
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if (status & TWI_SR_TXCOMP)
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sc->flags |= TWI_SR_TXCOMP;
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WR4(sc, TWI_IDR, status);
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wakeup(sc);
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AT91_TWI_UNLOCK(sc);
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return;
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}
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static int
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at91_twi_wait(struct at91_twi_softc *sc, uint32_t bit)
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{
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int err = 0;
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int counter = 100000;
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uint32_t sr;
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AT91_TWI_ASSERT_LOCKED(sc);
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while (!((sr = RD4(sc, TWI_SR)) & bit) && counter-- > 0 &&
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!(sr & TWI_SR_NACK))
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continue;
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if (counter <= 0)
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err = EBUSY;
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else if (sr & TWI_SR_NACK)
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err = ENXIO; // iic nack convention
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return (err);
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}
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static int
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at91_twi_rst_card(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
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{
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struct at91_twi_softc *sc;
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int clk;
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sc = device_get_softc(dev);
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AT91_TWI_LOCK(sc);
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if (oldaddr)
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*oldaddr = sc->twi_addr;
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sc->twi_addr = addr;
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/*
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* speeds are for 1.5kb/s, 45kb/s and 90kb/s.
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*/
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switch (speed) {
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case IIC_SLOW:
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clk = TWI_SLOW_CLOCK;
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break;
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case IIC_FAST:
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clk = TWI_FAST_CLOCK;
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break;
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case IIC_UNKNOWN:
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case IIC_FASTEST:
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default:
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clk = TWI_FASTEST_CLOCK;
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break;
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}
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sc->cwgr = TWI_CWGR_CKDIV(1) | TWI_CWGR_CHDIV(TWI_CWGR_DIV(clk)) |
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TWI_CWGR_CLDIV(TWI_CWGR_DIV(clk));
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WR4(sc, TWI_CR, TWI_CR_SWRST);
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WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
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WR4(sc, TWI_CWGR, sc->cwgr);
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printf("setting cwgr to %#x\n", sc->cwgr);
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AT91_TWI_UNLOCK(sc);
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return 0;
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}
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static int
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at91_twi_callback(device_t dev, int index, caddr_t data)
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{
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int error = 0;
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switch (index) {
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case IIC_REQUEST_BUS:
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break;
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case IIC_RELEASE_BUS:
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break;
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default:
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error = EINVAL;
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}
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return (error);
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}
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static int
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at91_twi_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
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{
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struct at91_twi_softc *sc;
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int i, len, err;
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uint32_t rdwr;
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uint8_t *buf;
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uint32_t sr;
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sc = device_get_softc(dev);
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err = 0;
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AT91_TWI_LOCK(sc);
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for (i = 0; i < nmsgs; i++) {
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/*
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* The linux atmel driver doesn't use the internal device
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* address feature of twi. A separate i2c message needs to
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* be written to use this.
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* See http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2004-September/024411.html
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* for details. Upon reflection, we could use this as an
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* optimization, but it is unclear the code bloat will
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* result in faster/better operations.
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*/
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rdwr = (msgs[i].flags & IIC_M_RD) ? TWI_MMR_MREAD : 0;
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WR4(sc, TWI_MMR, TWI_MMR_DADR(msgs[i].slave) | rdwr);
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len = msgs[i].len;
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buf = msgs[i].buf;
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/* zero byte transfers aren't allowed */
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if (len == 0 || buf == NULL) {
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err = EINVAL;
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goto out;
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}
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if (len == 1 && msgs[i].flags & IIC_M_RD)
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WR4(sc, TWI_CR, TWI_CR_START | TWI_CR_STOP);
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else
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WR4(sc, TWI_CR, TWI_CR_START);
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if (msgs[i].flags & IIC_M_RD) {
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sr = RD4(sc, TWI_SR);
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while (!(sr & TWI_SR_TXCOMP)) {
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if ((sr = RD4(sc, TWI_SR)) & TWI_SR_RXRDY) {
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len--;
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*buf++ = RD4(sc, TWI_RHR) & 0xff;
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if (len == 1)
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WR4(sc, TWI_CR, TWI_CR_STOP);
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}
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}
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if (len > 0 || (sr & TWI_SR_NACK)) {
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err = ENXIO; // iic nack convention
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goto out;
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}
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} else {
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while (len--) {
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if ((err = at91_twi_wait(sc, TWI_SR_TXRDY)))
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goto out;
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WR4(sc, TWI_THR, *buf++);
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}
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}
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if ((err = at91_twi_wait(sc, TWI_SR_TXCOMP)))
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break;
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}
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out:;
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if (err) {
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WR4(sc, TWI_CR, TWI_CR_SWRST);
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WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
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WR4(sc, TWI_CWGR, sc->cwgr);
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}
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AT91_TWI_UNLOCK(sc);
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return (err);
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}
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static device_method_t at91_twi_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, at91_twi_probe),
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DEVMETHOD(device_attach, at91_twi_attach),
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DEVMETHOD(device_detach, at91_twi_detach),
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/* iicbus interface */
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DEVMETHOD(iicbus_callback, at91_twi_callback),
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DEVMETHOD(iicbus_reset, at91_twi_rst_card),
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DEVMETHOD(iicbus_transfer, at91_twi_transfer),
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{ 0, 0 }
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};
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static driver_t at91_twi_driver = {
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"at91_twi",
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at91_twi_methods,
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sizeof(struct at91_twi_softc),
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};
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DRIVER_MODULE(at91_twi, atmelarm, at91_twi_driver, at91_twi_devclass, 0, 0);
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DRIVER_MODULE(iicbus, at91_twi, iicbus_driver, iicbus_devclass, 0, 0);
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MODULE_DEPEND(at91_twi, iicbus, 1, 1, 1);
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