61d2d8df78
This is a MIPS4KC CPU with various embedded peripherals, including wireless and ethernet support. This commit includes the platform, UART, ethernet MAC and GPIO support. The interrupt-driven GPIO code is disabled for now pending GPIO changes from the submitter. Submitted by: Aleksandr Rybalko <ray@dlink.ua>
508 lines
12 KiB
C
508 lines
12 KiB
C
/* $NetBSD: uart.c,v 1.2 2007/03/23 20:05:47 dogcow Exp $ */
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/*-
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* Copyright (c) 2010 Aleksandr Rybalko.
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* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
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* Copyright (c) 2007 Oleksandr Tymoshenko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kdb.h>
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#include <sys/reboot.h>
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#include <sys/sysctl.h>
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#include <sys/kernel.h>
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#include <machine/bus.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_bus.h>
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#include <mips/rt305x/uart_dev_rt305x.h>
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#include <mips/rt305x/rt305xreg.h>
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#include "uart_if.h"
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/*
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* Low-level UART interface.
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*/
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static int rt305x_uart_probe(struct uart_bas *bas);
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static void rt305x_uart_init(struct uart_bas *bas, int, int, int, int);
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static void rt305x_uart_term(struct uart_bas *bas);
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static void rt305x_uart_putc(struct uart_bas *bas, int);
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static int rt305x_uart_rxready(struct uart_bas *bas);
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static int rt305x_uart_getc(struct uart_bas *bas, struct mtx *);
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static struct uart_ops uart_rt305x_uart_ops = {
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.probe = rt305x_uart_probe,
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.init = rt305x_uart_init,
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.term = rt305x_uart_term,
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.putc = rt305x_uart_putc,
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.rxready = rt305x_uart_rxready,
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.getc = rt305x_uart_getc,
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};
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static int uart_output = 1;
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TUNABLE_INT("kern.uart_output", &uart_output);
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SYSCTL_INT(_kern, OID_AUTO, uart_output, CTLFLAG_RW,
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&uart_output, 0, "UART output enabled.");
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static int
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rt305x_uart_probe(struct uart_bas *bas)
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{
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return (0);
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}
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static void
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rt305x_uart_init(struct uart_bas *bas, int baudrate, int databits,
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int stopbits, int parity)
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{
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#ifdef notyet
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/* CLKDIV = 384000000/ 3/ 16/ br */
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/* for 384MHz CLKDIV = 8000000 / baudrate; */
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switch (databits) {
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case 5:
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databits = UART_LCR_5B;
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break;
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case 6:
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databits = UART_LCR_6B;
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break;
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case 7:
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databits = UART_LCR_7B;
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break;
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case 8:
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databits = UART_LCR_8B;
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break;
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default:
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/* Unsupported */
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return;
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}
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switch (parity) {
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case UART_PARITY_EVEN: parity = (UART_LCR_PEN|UART_LCR_EVEN); break;
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case UART_PARITY_NONE: parity = (UART_LCR_PEN); break;
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case UART_PARITY_ODD: parity = 0; break;
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/* Unsupported */
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default: return;
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}
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uart_setreg(bas, UART_CDDL_REG, 8000000/baudrate);
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uart_barrier(bas);
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uart_setreg(bas, UART_LCR_REG, databits | (stopbits==1?0:4) | parity);
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uart_barrier(bas);
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#endif
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}
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static void
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rt305x_uart_term(struct uart_bas *bas)
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{
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uart_setreg(bas, UART_MCR_REG, 0);
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uart_barrier(bas);
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}
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static void
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rt305x_uart_putc(struct uart_bas *bas, int c)
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{
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char chr;
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if (!uart_output) return;
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chr = c;
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while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));
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uart_setreg(bas, UART_TX_REG, c);
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uart_barrier(bas);
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while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));
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}
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static int
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rt305x_uart_rxready(struct uart_bas *bas)
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{
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#ifdef notyet
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if (uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)
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return (1);
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return (0);
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#else
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return (1);
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#endif
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}
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static int
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rt305x_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
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{
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int c;
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uart_lock(hwmtx);
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while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)) {
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uart_unlock(hwmtx);
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DELAY(10);
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uart_lock(hwmtx);
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}
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c = uart_getreg(bas, UART_RX_REG);
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uart_unlock(hwmtx);
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return (c);
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}
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/*
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* High-level UART interface.
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*/
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struct rt305x_uart_softc {
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struct uart_softc base;
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};
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static int rt305x_uart_bus_attach(struct uart_softc *);
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static int rt305x_uart_bus_detach(struct uart_softc *);
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static int rt305x_uart_bus_flush(struct uart_softc *, int);
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static int rt305x_uart_bus_getsig(struct uart_softc *);
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static int rt305x_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int rt305x_uart_bus_ipend(struct uart_softc *);
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static int rt305x_uart_bus_param(struct uart_softc *, int, int, int, int);
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static int rt305x_uart_bus_probe(struct uart_softc *);
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static int rt305x_uart_bus_receive(struct uart_softc *);
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static int rt305x_uart_bus_setsig(struct uart_softc *, int);
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static int rt305x_uart_bus_transmit(struct uart_softc *);
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static kobj_method_t rt305x_uart_methods[] = {
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KOBJMETHOD(uart_attach, rt305x_uart_bus_attach),
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KOBJMETHOD(uart_detach, rt305x_uart_bus_detach),
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KOBJMETHOD(uart_flush, rt305x_uart_bus_flush),
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KOBJMETHOD(uart_getsig, rt305x_uart_bus_getsig),
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KOBJMETHOD(uart_ioctl, rt305x_uart_bus_ioctl),
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KOBJMETHOD(uart_ipend, rt305x_uart_bus_ipend),
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KOBJMETHOD(uart_param, rt305x_uart_bus_param),
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KOBJMETHOD(uart_probe, rt305x_uart_bus_probe),
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KOBJMETHOD(uart_receive, rt305x_uart_bus_receive),
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KOBJMETHOD(uart_setsig, rt305x_uart_bus_setsig),
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KOBJMETHOD(uart_transmit, rt305x_uart_bus_transmit),
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{ 0, 0 }
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};
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struct uart_class uart_rt305x_uart_class = {
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"rt305x",
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rt305x_uart_methods,
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sizeof(struct rt305x_uart_softc),
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.uc_ops = &uart_rt305x_uart_ops,
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.uc_range = 1, /* use hinted range */
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.uc_rclk = SYSTEM_CLOCK
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};
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#define SIGCHG(c, i, s, d) \
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if (c) { \
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i |= (i & s) ? s : s | d; \
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} else { \
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i = (i & s) ? (i & ~s) | d : i; \
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}
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/*
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* Disable TX interrupt. uart should be locked
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*/
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static __inline void
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rt305x_uart_disable_txintr(struct uart_softc *sc)
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{
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struct uart_bas *bas = &sc->sc_bas;
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uint8_t cr;
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cr = uart_getreg(bas, UART_IER_REG);
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cr &= ~UART_IER_ETBEI;
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uart_setreg(bas, UART_IER_REG, cr);
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uart_barrier(bas);
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}
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/*
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* Enable TX interrupt. uart should be locked
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*/
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static __inline void
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rt305x_uart_enable_txintr(struct uart_softc *sc)
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{
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struct uart_bas *bas = &sc->sc_bas;
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uint8_t cr;
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cr = uart_getreg(bas, UART_IER_REG);
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cr |= UART_IER_ETBEI;
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uart_setreg(bas, UART_IER_REG, cr);
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uart_barrier(bas);
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}
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static int
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rt305x_uart_bus_attach(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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struct uart_devinfo *di;
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bas = &sc->sc_bas;
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if (sc->sc_sysdev != NULL) {
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di = sc->sc_sysdev;
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rt305x_uart_init(bas, di->baudrate, di->databits, di->stopbits,
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di->parity);
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} else {
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rt305x_uart_init(bas, 115200, 8, 1, 0);
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}
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sc->sc_rxfifosz = 16;
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sc->sc_txfifosz = 16;
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(void)rt305x_uart_bus_getsig(sc);
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/* Enable FIFO */
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uart_setreg(bas, UART_FCR_REG,
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uart_getreg(bas, UART_FCR_REG) |
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UART_FCR_FIFOEN | UART_FCR_TXTGR_1 | UART_FCR_RXTGR_1);
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uart_barrier(bas);
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/* Enable interrupts */
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uart_setreg(bas, UART_IER_REG,
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UART_IER_EDSSI | UART_IER_ELSI | UART_IER_ERBFI);
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uart_barrier(bas);
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return (0);
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}
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static int
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rt305x_uart_bus_detach(struct uart_softc *sc)
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{
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return (0);
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}
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static int
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rt305x_uart_bus_flush(struct uart_softc *sc, int what)
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{
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struct uart_bas *bas = &sc->sc_bas;
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uint32_t fcr = uart_getreg(bas, UART_FCR_REG);
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if (what & UART_FLUSH_TRANSMITTER) {
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uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_TXRST);
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uart_barrier(bas);
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}
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if (what & UART_FLUSH_RECEIVER) {
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uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_RXRST);
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uart_barrier(bas);
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}
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uart_setreg(bas, UART_FCR_REG, fcr);
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uart_barrier(bas);
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return (0);
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}
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static int
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rt305x_uart_bus_getsig(struct uart_softc *sc)
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{
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uint32_t new, old, sig;
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uint8_t bes;
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do {
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old = sc->sc_hwsig;
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sig = old;
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uart_lock(sc->sc_hwmtx);
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bes = uart_getreg(&sc->sc_bas, UART_MSR_REG);
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uart_unlock(sc->sc_hwmtx);
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/* XXX: chip can show delta */
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SIGCHG(bes & UART_MSR_CTS, sig, SER_CTS, SER_DCTS);
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SIGCHG(bes & UART_MSR_DCD, sig, SER_DCD, SER_DDCD);
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SIGCHG(bes & UART_MSR_DSR, sig, SER_DSR, SER_DDSR);
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new = sig & ~SER_MASK_DELTA;
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} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
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return (sig);
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}
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static int
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rt305x_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
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{
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struct uart_bas *bas;
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int baudrate, divisor, error;
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bas = &sc->sc_bas;
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error = 0;
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uart_lock(sc->sc_hwmtx);
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switch (request) {
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case UART_IOCTL_BREAK:
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/* TODO: Send BREAK */
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break;
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case UART_IOCTL_BAUD:
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divisor = uart_getreg(bas, UART_CDDL_REG);
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baudrate = bas->rclk / (divisor * 16);
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*(int*)data = baudrate;
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break;
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default:
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error = EINVAL;
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break;
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}
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uart_unlock(sc->sc_hwmtx);
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return (error);
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}
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static int
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rt305x_uart_bus_ipend(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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int ipend;
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uint8_t iir, lsr, msr;
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bas = &sc->sc_bas;
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ipend = 0;
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uart_lock(sc->sc_hwmtx);
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iir = uart_getreg(&sc->sc_bas, UART_IIR_REG);
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lsr = uart_getreg(&sc->sc_bas, UART_LSR_REG);
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uart_setreg(&sc->sc_bas, UART_LSR_REG, lsr);
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msr = uart_getreg(&sc->sc_bas, UART_MSR_REG);
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uart_setreg(&sc->sc_bas, UART_MSR_REG, msr);
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if (iir & UART_IIR_INTP) {
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uart_unlock(sc->sc_hwmtx);
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return (0);
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}
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switch ((iir >> 1) & 0x07) {
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case UART_IIR_ID_THRE:
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ipend |= SER_INT_TXIDLE;
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break;
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case UART_IIR_ID_DR2:
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rt305x_uart_bus_flush(sc, UART_FLUSH_RECEIVER);
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/* passthrough */
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case UART_IIR_ID_DR:
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ipend |= SER_INT_RXREADY;
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break;
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case UART_IIR_ID_MST:
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case UART_IIR_ID_LINESTATUS:
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ipend |= SER_INT_SIGCHG;
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if (lsr & UART_LSR_BI)
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{
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ipend |= SER_INT_BREAK;
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#ifdef KDB
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breakpoint();
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#endif
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}
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if (lsr & UART_LSR_OE)
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ipend |= SER_INT_OVERRUN;
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break;
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default:
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/* XXX: maybe return error here */
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break;
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}
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uart_unlock(sc->sc_hwmtx);
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return (ipend);
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}
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static int
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rt305x_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
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int stopbits, int parity)
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{
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uart_lock(sc->sc_hwmtx);
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rt305x_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
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uart_unlock(sc->sc_hwmtx);
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return (0);
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}
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static int
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rt305x_uart_bus_probe(struct uart_softc *sc)
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{
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char buf[80];
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int error;
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error = rt305x_uart_probe(&sc->sc_bas);
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if (error)
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return (error);
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snprintf(buf, sizeof(buf), "rt305x_uart");
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device_set_desc_copy(sc->sc_dev, buf);
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return (0);
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}
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static int
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rt305x_uart_bus_receive(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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int xc;
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uint8_t lsr;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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lsr = uart_getreg(bas, UART_LSR_REG);
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while ((lsr & UART_LSR_DR)) {
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if (uart_rx_full(sc)) {
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sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
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break;
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}
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xc = 0;
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xc = uart_getreg(bas, UART_RX_REG);
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if (lsr & UART_LSR_FE)
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xc |= UART_STAT_FRAMERR;
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if (lsr & UART_LSR_PE)
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xc |= UART_STAT_PARERR;
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if (lsr & UART_LSR_OE)
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xc |= UART_STAT_OVERRUN;
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uart_barrier(bas);
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uart_rx_put(sc, xc);
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lsr = uart_getreg(bas, UART_LSR_REG);
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}
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uart_unlock(sc->sc_hwmtx);
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return (0);
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}
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static int
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rt305x_uart_bus_setsig(struct uart_softc *sc, int sig)
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{
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/* TODO: implement (?) */
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return (0);
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}
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static int
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rt305x_uart_bus_transmit(struct uart_softc *sc)
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{
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struct uart_bas *bas = &sc->sc_bas;
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int i;
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|
|
if (!uart_output) return (0);
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
while ((uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE) == 0)
|
|
;
|
|
rt305x_uart_enable_txintr(sc);
|
|
for (i = 0; i < sc->sc_txdatasz; i++) {
|
|
uart_setreg(bas, UART_TX_REG, sc->sc_txbuf[i]);
|
|
uart_barrier(bas);
|
|
}
|
|
sc->sc_txbusy = 1;
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|