c48055dea1
associated comment as besides US-IV+ these bits are only available with US-III++, i.e. the 1.2GHz version of the US-III+.
71 lines
2.6 KiB
C
71 lines
2.6 KiB
C
/*-
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* Copyright (c) 2008 Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_DCR_H_
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#define _MACHINE_DCR_H_
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/*
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* Definitions for the UltraSPARC-III Depatch Control Register (ASR 18).
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*/
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#define DCR_MS (1UL << 0)
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#define DCR_IFPOE (1UL << 1)
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#define DCR_SI (1UL << 3)
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#define DCR_RPE (1UL << 4)
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#define DCR_BPE (1UL << 5)
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#define DCR_OBSDATA_SHIFT 6
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#define DCR_OBSDATA_CT_BITS 8
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#define DCR_OBSDATA_CT_MASK \
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(((1UL << DCR_OBSDATA_CT_BITS) - 1) << DCR_OBSDATA_SHIFT)
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/* The following bits are valid for the UltraSPARC-III++/IV+ only. */
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#define DCR_IPE (1UL << 2)
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#define DCR_OBSDATA_CTP_BITS 6
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#define DCR_OBSDATA_CTP_MASK \
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(((1UL << DCR_OBSDATA_CTP_BITS) - 1) << DCR_OBSDATA_SHIFT)
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#define DCR_DPE (1UL << 12)
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/* The following bits are valid for the UltraSPARC-IV+ only. */
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#define DCR_BPM_SHIFT 13
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#define DCR_BPM_BITS 2
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#define DCR_BPM_MASK \
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(((1UL << DCR_BPM_BITS) - 1) << DCR_BPM_SHIFT)
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#define DCR_BPM_1HIST_GSHARE (0UL << DCR_BPM_SHIFT)
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#define DCR_BPM_2HIST_GSHARE (1UL << DCR_BPM_SHIFT)
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#define DCR_BPM_PC (2UL << DCR_BPM_SHIFT)
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#define DCR_BPM_2HIST_MIXED (3UL << DCR_BPM_SHIFT)
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#define DCR_JPE (1UL << 15)
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#define DCR_ITPE (1UL << 16)
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#define DCR_DTPE (1UL << 17)
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#define DCR_PPE (1UL << 18)
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#endif /* _MACHINE_DCR_H_ */
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