6d4918e45e
(obvious in retrospect) in which interrupts on one CPU that are temporarily masked can end up permanently masked when a handler on another CPU clobbers the interrupt mask register with an old copy.
244 lines
6.2 KiB
C
244 lines
6.2 KiB
C
/*-
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* Copyright 2010 Nathan Whitehorn
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/platform.h>
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#include "ps3-hvcall.h"
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#include "pic_if.h"
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static void ps3pic_identify(driver_t *driver, device_t parent);
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static int ps3pic_probe(device_t);
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static int ps3pic_attach(device_t);
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static void ps3pic_dispatch(device_t, struct trapframe *);
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static void ps3pic_enable(device_t, u_int, u_int);
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static void ps3pic_eoi(device_t, u_int);
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static void ps3pic_ipi(device_t, u_int);
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static void ps3pic_mask(device_t, u_int);
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static void ps3pic_unmask(device_t, u_int);
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struct ps3pic_softc {
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volatile uint64_t *bitmap_thread0;
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volatile uint64_t *mask_thread0;
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volatile uint64_t *bitmap_thread1;
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volatile uint64_t *mask_thread1;
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uint64_t sc_ipi_outlet[2];
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int sc_vector[64];
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};
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static device_method_t ps3pic_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, ps3pic_identify),
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DEVMETHOD(device_probe, ps3pic_probe),
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DEVMETHOD(device_attach, ps3pic_attach),
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/* PIC interface */
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DEVMETHOD(pic_dispatch, ps3pic_dispatch),
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DEVMETHOD(pic_enable, ps3pic_enable),
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DEVMETHOD(pic_eoi, ps3pic_eoi),
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DEVMETHOD(pic_ipi, ps3pic_ipi),
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DEVMETHOD(pic_mask, ps3pic_mask),
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DEVMETHOD(pic_unmask, ps3pic_unmask),
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{ 0, 0 },
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};
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static driver_t ps3pic_driver = {
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"ps3pic",
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ps3pic_methods,
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sizeof(struct ps3pic_softc)
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};
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static devclass_t ps3pic_devclass;
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DRIVER_MODULE(ps3pic, nexus, ps3pic_driver, ps3pic_devclass, 0, 0);
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static MALLOC_DEFINE(M_PS3PIC, "ps3pic", "PS3 PIC");
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static void
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ps3pic_identify(driver_t *driver, device_t parent)
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{
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if (strcmp(installed_platform(), "ps3") != 0)
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return;
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if (device_find_child(parent, "ps3pic", -1) == NULL)
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BUS_ADD_CHILD(parent, 0, "ps3pic", 0);
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}
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static int
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ps3pic_probe(device_t dev)
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{
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device_set_desc(dev, "Playstation 3 interrupt controller");
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return (BUS_PROBE_NOWILDCARD);
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}
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static int
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ps3pic_attach(device_t dev)
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{
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struct ps3pic_softc *sc;
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uint64_t ppe;
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int thread;
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sc = device_get_softc(dev);
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sc->bitmap_thread0 = contigmalloc(128 /* 512 bits * 2 */, M_PS3PIC,
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M_NOWAIT | M_ZERO, 0, BUS_SPACE_MAXADDR, 64 /* alignment */,
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PAGE_SIZE /* boundary */);
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sc->mask_thread0 = sc->bitmap_thread0 + 4;
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sc->bitmap_thread1 = sc->bitmap_thread0 + 8;
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sc->mask_thread1 = sc->bitmap_thread0 + 12;
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lv1_get_logical_ppe_id(&ppe);
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thread = 32 - fls(mfctrl());
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lv1_configure_irq_state_bitmap(ppe, thread,
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vtophys(sc->bitmap_thread0));
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#ifdef SMP
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lv1_configure_irq_state_bitmap(ppe, !thread,
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vtophys(sc->bitmap_thread1));
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/* Map both IPIs to the same VIRQ to avoid changes in intr_machdep */
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lv1_construct_event_receive_port(&sc->sc_ipi_outlet[0]);
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lv1_connect_irq_plug_ext(ppe, thread, sc->sc_ipi_outlet[0],
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sc->sc_ipi_outlet[0], 0);
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lv1_construct_event_receive_port(&sc->sc_ipi_outlet[1]);
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lv1_connect_irq_plug_ext(ppe, !thread, sc->sc_ipi_outlet[0],
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sc->sc_ipi_outlet[1], 0);
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#endif
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powerpc_register_pic(dev, 0, sc->sc_ipi_outlet[0], 1, FALSE);
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return (0);
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}
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/*
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* PIC I/F methods.
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*/
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static void
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ps3pic_dispatch(device_t dev, struct trapframe *tf)
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{
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uint64_t bitmap, mask;
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int irq;
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struct ps3pic_softc *sc;
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sc = device_get_softc(dev);
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if (PCPU_GET(cpuid) == 0) {
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bitmap = sc->bitmap_thread0[0];
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mask = sc->mask_thread0[0];
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} else {
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bitmap = sc->bitmap_thread1[0];
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mask = sc->mask_thread1[0];
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}
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while ((irq = ffsl(bitmap & mask) - 1) != -1) {
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bitmap &= ~(1UL << irq);
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powerpc_dispatch_intr(sc->sc_vector[63 - irq], tf);
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}
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}
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static void
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ps3pic_enable(device_t dev, u_int irq, u_int vector)
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{
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struct ps3pic_softc *sc;
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sc = device_get_softc(dev);
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sc->sc_vector[irq] = vector;
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ps3pic_unmask(dev, irq);
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}
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static void
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ps3pic_eoi(device_t dev, u_int irq)
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{
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uint64_t ppe;
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int thread;
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lv1_get_logical_ppe_id(&ppe);
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thread = 32 - fls(mfctrl());
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lv1_end_of_interrupt_ext(ppe, thread, irq);
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}
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static void
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ps3pic_ipi(device_t dev, u_int cpu)
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{
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struct ps3pic_softc *sc;
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sc = device_get_softc(dev);
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lv1_send_event_locally(sc->sc_ipi_outlet[cpu]);
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}
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static void
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ps3pic_mask(device_t dev, u_int irq)
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{
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struct ps3pic_softc *sc;
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uint64_t ppe;
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sc = device_get_softc(dev);
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/* Do not mask IPIs! */
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if (irq == sc->sc_ipi_outlet[0])
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return;
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atomic_clear_64(&sc->mask_thread0[0], 1UL << (63 - irq));
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atomic_clear_64(&sc->mask_thread1[0], 1UL << (63 - irq));
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lv1_get_logical_ppe_id(&ppe);
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lv1_did_update_interrupt_mask(ppe, 0);
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lv1_did_update_interrupt_mask(ppe, 1);
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}
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static void
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ps3pic_unmask(device_t dev, u_int irq)
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{
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struct ps3pic_softc *sc;
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uint64_t ppe;
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sc = device_get_softc(dev);
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atomic_set_64(&sc->mask_thread0[0], 1UL << (63 - irq));
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atomic_set_64(&sc->mask_thread1[0], 1UL << (63 - irq));
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lv1_get_logical_ppe_id(&ppe);
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lv1_did_update_interrupt_mask(ppe, 0);
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lv1_did_update_interrupt_mask(ppe, 1);
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}
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