d82bc4fba8
internal PHY on the 3COM 3C905B and 3C905C parts, however I've rigged it so that xlphy (aka exphy) takes precedence for the time being. If people try this with their xl cards and decide that it's a better choice, we can switch this later. This is the PHY used in various iMacs and possibly other GMAC-equipped Macintoshes with 10/100 PHYs (the ones with 10/100/1000 appear to use brgphy). Obtained from: NetBSD
183 lines
7.9 KiB
C
183 lines
7.9 KiB
C
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* from NetBSD: bmtphyreg.h,v 1.1 2001/06/02 21:42:10 thorpej Exp
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_MII_BMTPHYREG_H_
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#define _DEV_MII_BMTPHYREG_H_
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/*
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* BCM5201/BCM5202 registers.
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*/
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#define MII_BMTPHY_AUX_CTL 0x10 /* auxiliary control */
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#define AUX_CTL_TXDIS 0x2000 /* transmitter disable */
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#define AUX_CTL_4B5B_BYPASS 0x0400 /* bypass 4b5b encoder */
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#define AUX_CTL_SCR_BYPASS 0x0200 /* bypass scrambler */
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#define AUX_CTL_NRZI_BYPASS 0x0100 /* bypass NRZI encoder */
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#define AUX_CTL_RXALIGN_BYPASS 0x0080 /* bypass rx symbol alignment */
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#define AUX_CTL_BASEWANDER_DIS 0x0040 /* disable baseline wander correction */
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#define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */
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#define MII_BMTPHY_AUX_STS 0x11 /* auxiliary status */
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#define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */
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#define AUX_STS_LOCKED 0x0200 /* descrambler locked */
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#define AUX_STS_100BASE_LINK 0x0100 /* 1 = 100base link */
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#define AUX_STS_REMFAULT 0x0080 /* remote fault */
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#define AUX_STS_DISCON_STATE 0x0040 /* disconnect state */
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#define AUX_STS_FCARDET 0x0020 /* false carrier detected */
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#define AUX_STS_BAD_ESD 0x0010 /* bad ESD detected */
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#define AUX_STS_RXERROR 0x0008 /* Rx error detected */
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#define AUX_STS_TXERROR 0x0004 /* Tx error detected */
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#define AUX_STS_LOCKERROR 0x0002 /* lock error detected */
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#define AUX_STS_MLT3ERROR 0x0001 /* MLT3 code error detected */
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#define MII_BMTPHY_RXERROR_CTR 0x12 /* 100base-X Rx error counter */
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#define RXERROR_CTR_MASK 0x00ff
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#define MII_BMTPHY_FCS_CTR 0x13 /* 100base-X false carrier counter */
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#define FCS_CTR_MASK 0x00ff
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#define MII_BMTPHY_DIS_CTR 0x14 /* 100base-X disconnect counter */
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#define DIS_CTR_MASK 0x00ff
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#define MII_BMTPHY_PTEST 0x17 /* PTEST */
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#define MII_BMTPHY_AUX_CSR 0x18 /* auxiliary control/status */
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#define AUX_CSR_JABBER_DIS 0x8000 /* jabber disable */
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#define AUX_CSR_FLINK 0x4000 /* force 10baseT link pass */
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#define AUX_CSR_HSQ 0x0080 /* SQ high */
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#define AUX_CSR_LSQ 0x0040 /* SQ low */
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#define AUX_CSR_ER1 0x0020 /* edge rate 1 */
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#define AUX_CSR_ER0 0x0010 /* edge rate 0 */
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#define AUX_CSR_ANEG 0x0008 /* auto-negotiation activated */
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#define AUX_CSR_F100 0x0004 /* force 100base */
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#define AUX_CSR_SPEED 0x0002 /* 1 = 100, 0 = 10 */
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#define AUX_CSR_FDX 0x0001 /* full-duplex */
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#define MII_BMTPHY_AUX_SS 0x19 /* auxiliary status summary */
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#define AUX_SS_ACOMP 0x8000 /* auto-negotiation complete */
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#define AUX_SS_ACOMP_ACK 0x4000 /* auto-negotiation compl. ack */
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#define AUX_SS_AACK_DET 0x2000 /* auto-neg. ack detected */
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#define AUX_SS_ANLPAD 0x1000 /* auto-neg. link part. ability det */
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#define AUX_SS_ANEG_PAUSE 0x0800 /* pause operation bit */
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#define AUX_SS_HCD 0x0700 /* highest common denominator */
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#define AUX_SS_HCD_NONE 0x0000 /* none */
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#define AUX_SS_HCD_10T 0x0100 /* 10baseT */
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#define AUX_SS_HCD_10T_FDX 0x0200 /* 10baseT-FDX */
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#define AUX_SS_HCD_100TX 0x0300 /* 100baseTX-FDX */
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#define AUX_SS_HCD_100T4 0x0400 /* 100baseT4 */
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#define AUX_SS_HCD_100TX_FDX 0x0500 /* 100baseTX-FDX */
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#define AUX_SS_PDF 0x0080 /* parallel detection fault */
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#define AUX_SS_LPRF 0x0040 /* link partner remote fault */
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#define AUX_SS_LPPR 0x0020 /* link partner page received */
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#define AUX_SS_LPANA 0x0010 /* link partner auto-neg able */
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#define AUX_SS_SPEED 0x0008 /* 1 = 100, 0 = 10 */
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#define AUX_SS_LINK 0x0004 /* link pass */
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#define AUX_SS_ANEN 0x0002 /* auto-neg. enabled */
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#define AUX_SS_JABBER 0x0001 /* jabber detected */
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#define MII_BMTPHY_INTR 0x1a /* interrupt register */
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#define INTR_FDX_LED 0x8000 /* full-duplex led enable */
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#define INTR_INTR_EN 0x4000 /* interrupt enable */
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#define INTR_FDX_MASK 0x0800 /* full-dupled intr mask */
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#define INTR_SPD_MASK 0x0400 /* speed intr mask */
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#define INTR_LINK_MASK 0x0200 /* link intr mask */
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#define INTR_INTR_MASK 0x0100 /* master interrupt mask */
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#define INTR_FDX_CHANGE 0x0008 /* full-duplex change */
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#define INTR_SPD_CHANGE 0x0004 /* speed change */
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#define INTR_LINK_CHANGE 0x0002 /* link change */
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#define INTR_INTR_STATUS 0x0001 /* interrupt status */
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#define MII_BMTPHY_AUX2 0x1b /* auliliary mode 2 */
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#define AUX2_BLOCK_RXDV 0x0200 /* block RXDV mode enabled */
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#define AUX2_ANPDQ 0x0100 /* auto-neg parallel detection Q mode */
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#define AUX2_TRAFFIC_LED 0x0040 /* traffic meter led enable */
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#define AUX2_FXMTRCV_LED 0x0020 /* force Tx and Rx LEDs */
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#define AUX2_HS_TOKEN 0x0010 /* high-speed token ring mode */
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#define AUX2_AUTO_LP 0x0008 /* auto low-power mode */
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#define AUX2_TWOLINK_LED 0x0004 /* two link LEDs */
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#define AUX2_SQE_DIS 0x0002 /* disable SQE pulse */
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#define MII_BMTPHY_AUXERR 0x1c /* auxiliary error */
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#define AUXERR_MANCHESTER 0x0400 /* Manchester code error */
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#define AUXERR_EOF 0x0200 /* EOF detection error */
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#define AUXERR_POLARITY 0x0100 /* polarity inversion */
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#define AUXERR_ANEG 0x0008 /* autonegotiation enabled */
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#define AUXERR_F100 0x0004 /* force 100base */
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#define AUXERR_SPEED 0x0002 /* 1 = 100, 0 = 10 */
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#define AUXERR_FDX 0x0001 /* full-duplex */
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#define MII_BMTPHY_AUXMODE 0x1d /* auxiliary mode */
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#define AUXMODE_ACT_LED_DIS 0x0010 /* activity LED disable */
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#define AUXMODE_LINK_LED_DIS 0x0008 /* link LED disable */
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#define AUXMODE_BLOCK_TXEN 0x0002 /* enable block TXEN */
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#define MII_BMTPHY_AUXMPHY 0x1e /* auxiliary multiple phy register */
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#define AUXMPHY_HCD_TX_FDX 0x8000 /* res. is 100baseTX-FDX */
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#define AUXMPHY_HCD_T4 0x4000 /* res. is 100baseT4 */
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#define AUXMPHY_HCD_TX 0x2000 /* res. is 100baseTX */
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#define AUXMPHY_HCD_10T_FDX 0x1000 /* res. is 10baseT-FDX */
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#define AUXMPHY_HCD_10T 0x0800 /* res. is 10baseT */
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#define AUXMPHY_RES_ANEG 0x0100 /* restart auto-negotiation */
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#define AUXMPHY_ANEG_COMP 0x0080 /* auto-negotiation complete */
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#define AUXMPHY_ACK_COMP 0x0040 /* acknowledge complete */
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#define AUXMPHY_ACK_DET 0x0020 /* acknowledge detected */
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#define AUXMPHY_ABILITY_DET 0x0010 /* waiting for LP ability */
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#define AUXMPHY_SUPER_ISO 0x0008 /* super-isolate mode */
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#define AUXMPHY_10T_SERIAL 0x0002 /* 10baseT serial mode */
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#define MII_BMTPHY_TEST 0x1d /* Broadcom test register */
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#endif /* _DEV_MII_BMTPHYREG_H_ */
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