cdfefa0ba0
facilities as well as support for the Octeon 2 family of SoCs. XXX Note that with our antediluvian assembler, we can't support some Octeon 2 instructions and fall back to using the old ones instead.
240 lines
7.2 KiB
C
240 lines
7.2 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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#include <linux/module.h>
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#include <asm/octeon/cvmx.h>
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#include <asm/octeon/cvmx-debug.h>
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#include <asm/octeon/cvmx-uart.h>
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#include <asm/octeon/octeon-boot-info.h>
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#include <asm/octeon/cvmx-spinlock.h>
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int cvmx_debug_uart = 1;
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#else
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#include <limits.h>
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#include "executive-config.h"
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#include "cvmx.h"
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#include "cvmx-debug.h"
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#include "cvmx-uart.h"
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#include "cvmx-spinlock.h"
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#ifndef __OCTEON_NEWLIB__
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#include "../../bootloader/u-boot/include/octeon_mem_map.h"
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#else
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#include "octeon-boot-info.h"
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#endif
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#endif
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#ifdef __OCTEON_NEWLIB__
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#pragma weak cvmx_uart_enable_intr
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int cvmx_debug_uart = 1;
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#endif
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/* Default to second uart port for backward compatibility. The default (if
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-debug does not set the uart number) can now be overridden with
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CVMX_DEBUG_COMM_UART_NUM. */
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#ifndef CVMX_DEBUG_COMM_UART_NUM
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# define CVMX_DEBUG_COMM_UART_NUM 1
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#endif
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static CVMX_SHARED cvmx_spinlock_t cvmx_debug_uart_lock;
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/**
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* Interrupt handler for debugger Control-C interrupts.
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*
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* @param irq_number IRQ interrupt number
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* @param registers CPU registers at the time of the interrupt
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* @param user_arg Unused user argument
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*/
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void cvmx_debug_uart_process_debug_interrupt(int irq_number, uint64_t registers[32], void *user_arg)
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{
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cvmx_uart_lsr_t lsrval;
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/* Check for a Control-C interrupt from the debugger. This loop will eat
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all input received on the uart */
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lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(cvmx_debug_uart));
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while (lsrval.s.dr)
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{
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int c = cvmx_read_csr(CVMX_MIO_UARTX_RBR(cvmx_debug_uart));
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if (c == '\003')
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{
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register uint64_t tmp;
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#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
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fflush(stderr);
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fflush(stdout);
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#endif
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/* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also
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set the MCD0 to be not masked by this core so we know
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the signal is received by someone */
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asm volatile (
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"dmfc0 %0, $22\n"
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"ori %0, %0, 0x1110\n"
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"dmtc0 %0, $22\n"
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: "=r" (tmp));
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}
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lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(cvmx_debug_uart));
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}
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}
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static void cvmx_debug_uart_init(void)
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{
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if (cvmx_debug_uart == -1)
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cvmx_debug_uart = CVMX_DEBUG_COMM_UART_NUM;
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}
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static void cvmx_debug_uart_install_break_handler(void)
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{
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#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
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#ifdef __OCTEON_NEWLIB__
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if (cvmx_uart_enable_intr)
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#endif
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cvmx_uart_enable_intr(cvmx_debug_uart, cvmx_debug_uart_process_debug_interrupt);
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#endif
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}
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/* Get a packet from the UART, return 0 on failure and 1 on success. */
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static int cvmx_debug_uart_getpacket(char *buffer, size_t size)
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{
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while (1)
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{
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unsigned char checksum;
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int timedout = 0;
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size_t count;
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char ch;
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ch = cvmx_uart_read_byte_with_timeout(cvmx_debug_uart, &timedout, __SHRT_MAX__);
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if (timedout)
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return 0;
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/* if this is not the start character, ignore it. */
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if (ch != '$')
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continue;
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retry:
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checksum = 0;
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count = 0;
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/* now, read until a # or end of buffer is found */
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while (count < size)
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{
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ch = cvmx_uart_read_byte(cvmx_debug_uart);
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if (ch == '$')
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goto retry;
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if (ch == '#')
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break;
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checksum = checksum + ch;
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buffer[count] = ch;
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count = count + 1;
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}
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buffer[count] = 0;
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if (ch == '#')
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{
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char csumchars[2];
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unsigned xmitcsum;
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int n;
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csumchars[0] = cvmx_uart_read_byte(cvmx_debug_uart);
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csumchars[1] = cvmx_uart_read_byte(cvmx_debug_uart);
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n = sscanf(csumchars, "%2x", &xmitcsum);
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if (n != 1)
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return 1;
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return checksum == xmitcsum;
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}
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}
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return 0;
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}
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static int cvmx_debug_uart_putpacket(char *packet)
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{
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size_t i;
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unsigned char csum;
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unsigned char *ptr = (unsigned char *) packet;
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char csumstr[3];
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for (csum = 0, i = 0; ptr[i]; i++)
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csum += ptr[i];
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sprintf(csumstr, "%02x", csum);
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cvmx_spinlock_lock(&cvmx_debug_uart_lock);
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cvmx_uart_write_byte(cvmx_debug_uart, '$');
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cvmx_uart_write_string(cvmx_debug_uart, packet);
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cvmx_uart_write_byte(cvmx_debug_uart, '#');
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cvmx_uart_write_string(cvmx_debug_uart, csumstr);
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cvmx_spinlock_unlock(&cvmx_debug_uart_lock);
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return 0;
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}
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static void cvmx_debug_uart_change_core(int oldcore, int newcore)
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{
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#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
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cvmx_ciu_intx0_t irq_control;
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irq_control.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(newcore * 2));
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irq_control.s.uart |= (1<<cvmx_debug_uart);
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cvmx_write_csr(CVMX_CIU_INTX_EN0(newcore * 2), irq_control.u64);
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/* Disable interrupts to this core since he is about to die */
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irq_control.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(oldcore * 2));
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irq_control.s.uart &= ~(1<<cvmx_debug_uart);
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cvmx_write_csr(CVMX_CIU_INTX_EN0(oldcore* 2), irq_control.u64);
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#endif
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}
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cvmx_debug_comm_t cvmx_debug_uart_comm =
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{
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.init = cvmx_debug_uart_init,
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.install_break_handler = cvmx_debug_uart_install_break_handler,
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.needs_proxy = 1,
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.getpacket = cvmx_debug_uart_getpacket,
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.putpacket = cvmx_debug_uart_putpacket,
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.wait_for_resume = NULL,
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.change_core = cvmx_debug_uart_change_core,
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};
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