513 lines
13 KiB
C
513 lines
13 KiB
C
/*-
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* Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org>
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* Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org>
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* Copyright (c) 2009 Jung-uk Kim <jkim@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for the AMD CPU on-die thermal sensors for Family 0Fh/10h/11h procs.
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* Initially based on the k8temp Linux driver.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <machine/cpufunc.h>
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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#include <dev/pci/pcivar.h>
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typedef enum {
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SENSOR0_CORE0,
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SENSOR0_CORE1,
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SENSOR1_CORE0,
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SENSOR1_CORE1,
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CORE0,
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CORE1
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} amdsensor_t;
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struct amdtemp_softc {
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device_t sc_dev;
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int sc_ncores;
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int sc_ntemps;
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int sc_flags;
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#define AMDTEMP_FLAG_DO_QUIRK 0x01 /* DiodeOffset may be incorrect. */
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#define AMDTEMP_FLAG_DO_ZERO 0x02 /* DiodeOffset starts from 0C. */
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#define AMDTEMP_FLAG_DO_SIGN 0x04 /* DiodeOffsetSignBit is present. */
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#define AMDTEMP_FLAG_CS_SWAP 0x08 /* ThermSenseCoreSel is inverted. */
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#define AMDTEMP_FLAG_CT_10BIT 0x10 /* CurTmp is 10-bit wide. */
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int32_t (*sc_gettemp)(device_t, amdsensor_t);
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struct sysctl_oid *sc_sysctl_cpu[MAXCPU];
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struct intr_config_hook sc_ich;
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};
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#define VENDORID_AMD 0x1022
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#define DEVICEID_AMD_MISC0F 0x1103
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#define DEVICEID_AMD_MISC10 0x1203
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#define DEVICEID_AMD_MISC11 0x1303
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static struct amdtemp_product {
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uint16_t amdtemp_vendorid;
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uint16_t amdtemp_deviceid;
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} amdtemp_products[] = {
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{ VENDORID_AMD, DEVICEID_AMD_MISC0F },
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{ VENDORID_AMD, DEVICEID_AMD_MISC10 },
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{ VENDORID_AMD, DEVICEID_AMD_MISC11 },
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{ 0, 0 }
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};
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/*
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* Reported Temperature Control Register (Family 10h/11h only)
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*/
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#define AMDTEMP_REPTMP_CTRL 0xa4
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/*
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* Thermaltrip Status Register
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*/
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#define AMDTEMP_THERMTP_STAT 0xe4
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#define AMDTEMP_TTSR_SELCORE 0x04 /* Family 0Fh only */
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#define AMDTEMP_TTSR_SELSENSOR 0x40 /* Family 0Fh only */
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/*
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* CPU Family/Model Register
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*/
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#define AMDTEMP_CPUID 0xfc
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/*
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* Device methods.
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*/
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static void amdtemp_identify(driver_t *driver, device_t parent);
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static int amdtemp_probe(device_t dev);
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static int amdtemp_attach(device_t dev);
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static void amdtemp_intrhook(void *arg);
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static int amdtemp_detach(device_t dev);
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static int amdtemp_match(device_t dev);
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static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor);
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static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor);
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static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS);
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static device_method_t amdtemp_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, amdtemp_identify),
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DEVMETHOD(device_probe, amdtemp_probe),
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DEVMETHOD(device_attach, amdtemp_attach),
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DEVMETHOD(device_detach, amdtemp_detach),
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{0, 0}
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};
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static driver_t amdtemp_driver = {
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"amdtemp",
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amdtemp_methods,
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sizeof(struct amdtemp_softc),
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};
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static devclass_t amdtemp_devclass;
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DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, amdtemp_devclass, NULL, NULL);
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static int
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amdtemp_match(device_t dev)
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{
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int i;
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uint16_t vendor, devid;
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vendor = pci_get_vendor(dev);
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devid = pci_get_device(dev);
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for (i = 0; amdtemp_products[i].amdtemp_vendorid != 0; i++) {
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if (vendor == amdtemp_products[i].amdtemp_vendorid &&
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devid == amdtemp_products[i].amdtemp_deviceid)
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return (1);
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}
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return (0);
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}
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static void
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amdtemp_identify(driver_t *driver, device_t parent)
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{
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device_t child;
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/* Make sure we're not being doubly invoked. */
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if (device_find_child(parent, "amdtemp", -1) != NULL)
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return;
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if (amdtemp_match(parent)) {
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child = device_add_child(parent, "amdtemp", -1);
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if (child == NULL)
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device_printf(parent, "add amdtemp child failed\n");
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}
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}
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static int
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amdtemp_probe(device_t dev)
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{
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uint32_t family, model;
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if (resource_disabled("amdtemp", 0))
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return (ENXIO);
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family = CPUID_TO_FAMILY(cpu_id);
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model = CPUID_TO_MODEL(cpu_id);
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switch (family) {
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case 0x0f:
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if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) ||
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(model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1))
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return (ENXIO);
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break;
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case 0x10:
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case 0x11:
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break;
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default:
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return (ENXIO);
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}
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device_set_desc(dev, "AMD CPU On-Die Thermal Sensors");
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return (BUS_PROBE_GENERIC);
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}
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static int
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amdtemp_attach(device_t dev)
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{
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struct amdtemp_softc *sc = device_get_softc(dev);
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struct sysctl_ctx_list *sysctlctx;
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struct sysctl_oid *sysctlnode;
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uint32_t regs[4];
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uint32_t cpuid, family, model;
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/*
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* Errata #154: Incorect Diode Offset
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*/
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if (cpu_id == 0x20f32) {
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do_cpuid(0x80000001, regs);
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if ((regs[1] & 0xfff) == 0x2c)
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sc->sc_flags |= AMDTEMP_FLAG_DO_QUIRK;
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}
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/*
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* CPUID Register is available from Revision F.
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*/
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family = CPUID_TO_FAMILY(cpu_id);
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model = CPUID_TO_MODEL(cpu_id);
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if (family != 0x0f || model >= 0x40) {
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cpuid = pci_read_config(dev, AMDTEMP_CPUID, 4);
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family = CPUID_TO_FAMILY(cpuid);
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model = CPUID_TO_MODEL(cpuid);
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}
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switch (family) {
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case 0x0f:
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/*
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* Thermaltrip Status Register
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*
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* - DiodeOffsetSignBit
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*
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* Revision D & E: bit 24
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* Other: N/A
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*
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* - ThermSenseCoreSel
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*
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* Revision F & G: 0 - Core1, 1 - Core0
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* Other: 0 - Core0, 1 - Core1
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*
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* - CurTmp
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*
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* Revision G: bits 23-14
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* Other: bits 23-16
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*
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* XXX According to the BKDG, CurTmp, ThermSenseSel and
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* ThermSenseCoreSel bits were introduced in Revision F
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* but CurTmp seems working fine as early as Revision C.
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* However, it is not clear whether ThermSenseSel and/or
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* ThermSenseCoreSel work in undocumented cases as well.
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* In fact, the Linux driver suggests it may not work but
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* we just assume it does until we find otherwise.
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*/
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if (model < 0x40) {
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sc->sc_flags |= AMDTEMP_FLAG_DO_ZERO;
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if (model >= 0x10)
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sc->sc_flags |= AMDTEMP_FLAG_DO_SIGN;
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} else {
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sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP;
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if (model >= 0x60 && model != 0xc1)
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sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT;
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}
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/*
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* There are two sensors per core.
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*/
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sc->sc_ntemps = 2;
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sc->sc_gettemp = amdtemp_gettemp0f;
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break;
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case 0x10:
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case 0x11:
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/*
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* There is only one sensor per package.
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*/
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sc->sc_ntemps = 1;
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sc->sc_gettemp = amdtemp_gettemp;
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break;
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}
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/* Find number of cores per package. */
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sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ?
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(cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1;
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if (sc->sc_ncores > MAXCPU)
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return (ENXIO);
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if (bootverbose)
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device_printf(dev, "Found %d cores and %d sensors.\n",
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sc->sc_ncores,
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sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1);
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/*
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* dev.amdtemp.N tree.
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*/
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sysctlctx = device_get_sysctl_ctx(dev);
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sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
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SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
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"sensor0", CTLFLAG_RD, 0, "Sensor 0");
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SYSCTL_ADD_PROC(sysctlctx,
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SYSCTL_CHILDREN(sysctlnode),
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OID_AUTO, "core0", CTLTYPE_INT | CTLFLAG_RD,
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dev, SENSOR0_CORE0, amdtemp_sysctl, "IK",
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"Sensor 0 / Core 0 temperature");
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if (sc->sc_ntemps > 1) {
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if (sc->sc_ncores > 1)
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SYSCTL_ADD_PROC(sysctlctx,
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SYSCTL_CHILDREN(sysctlnode),
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OID_AUTO, "core1", CTLTYPE_INT | CTLFLAG_RD,
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dev, SENSOR0_CORE1, amdtemp_sysctl, "IK",
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"Sensor 0 / Core 1 temperature");
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sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
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SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
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"sensor1", CTLFLAG_RD, 0, "Sensor 1");
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SYSCTL_ADD_PROC(sysctlctx,
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SYSCTL_CHILDREN(sysctlnode),
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OID_AUTO, "core0", CTLTYPE_INT | CTLFLAG_RD,
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dev, SENSOR1_CORE0, amdtemp_sysctl, "IK",
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"Sensor 1 / Core 0 temperature");
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if (sc->sc_ncores > 1)
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SYSCTL_ADD_PROC(sysctlctx,
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SYSCTL_CHILDREN(sysctlnode),
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OID_AUTO, "core1", CTLTYPE_INT | CTLFLAG_RD,
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dev, SENSOR1_CORE1, amdtemp_sysctl, "IK",
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"Sensor 1 / Core 1 temperature");
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}
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/*
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* Try to create dev.cpu sysctl entries and setup intrhook function.
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* This is needed because the cpu driver may be loaded late on boot,
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* after us.
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*/
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amdtemp_intrhook(dev);
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sc->sc_ich.ich_func = amdtemp_intrhook;
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sc->sc_ich.ich_arg = dev;
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if (config_intrhook_establish(&sc->sc_ich) != 0) {
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device_printf(dev, "config_intrhook_establish failed!\n");
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return (ENXIO);
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}
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return (0);
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}
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void
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amdtemp_intrhook(void *arg)
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{
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struct amdtemp_softc *sc;
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struct sysctl_ctx_list *sysctlctx;
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device_t dev = (device_t)arg;
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device_t acpi, cpu, nexus;
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amdsensor_t sensor;
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int i;
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sc = device_get_softc(dev);
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/*
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* dev.cpu.N.temperature.
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*/
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nexus = device_find_child(root_bus, "nexus", 0);
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acpi = device_find_child(nexus, "acpi", 0);
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for (i = 0; i < sc->sc_ncores; i++) {
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if (sc->sc_sysctl_cpu[i] != NULL)
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continue;
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cpu = device_find_child(acpi, "cpu",
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device_get_unit(dev) * sc->sc_ncores + i);
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if (cpu != NULL) {
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sysctlctx = device_get_sysctl_ctx(cpu);
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sensor = sc->sc_ntemps > 1 ?
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(i == 0 ? CORE0 : CORE1) : SENSOR0_CORE0;
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sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx,
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SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)),
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OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD,
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dev, sensor, amdtemp_sysctl, "IK",
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"Current temparature");
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}
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}
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if (sc->sc_ich.ich_arg != NULL)
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config_intrhook_disestablish(&sc->sc_ich);
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}
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int
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amdtemp_detach(device_t dev)
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{
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struct amdtemp_softc *sc = device_get_softc(dev);
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int i;
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for (i = 0; i < sc->sc_ncores; i++)
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if (sc->sc_sysctl_cpu[i] != NULL)
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sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0);
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/* NewBus removes the dev.amdtemp.N tree by itself. */
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return (0);
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}
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static int
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amdtemp_sysctl(SYSCTL_HANDLER_ARGS)
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{
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device_t dev = (device_t)arg1;
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struct amdtemp_softc *sc = device_get_softc(dev);
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amdsensor_t sensor = (amdsensor_t)arg2;
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int32_t auxtemp[2], temp;
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int error;
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switch (sensor) {
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case CORE0:
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auxtemp[0] = sc->sc_gettemp(dev, SENSOR0_CORE0);
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auxtemp[1] = sc->sc_gettemp(dev, SENSOR1_CORE0);
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temp = imax(auxtemp[0], auxtemp[1]);
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break;
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case CORE1:
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auxtemp[0] = sc->sc_gettemp(dev, SENSOR0_CORE1);
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auxtemp[1] = sc->sc_gettemp(dev, SENSOR1_CORE1);
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temp = imax(auxtemp[0], auxtemp[1]);
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break;
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default:
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temp = sc->sc_gettemp(dev, sensor);
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break;
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}
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error = sysctl_handle_int(oidp, &temp, 0, req);
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return (error);
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}
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#define AMDTEMP_ZERO_C_TO_K 2732
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static int32_t
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amdtemp_gettemp0f(device_t dev, amdsensor_t sensor)
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{
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struct amdtemp_softc *sc = device_get_softc(dev);
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uint32_t mask, temp;
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int32_t diode_offset, offset;
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uint8_t cfg, sel;
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/* Set Sensor/Core selector. */
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sel = 0;
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switch (sensor) {
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case SENSOR1_CORE0:
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sel |= AMDTEMP_TTSR_SELSENSOR;
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/* FALLTHROUGH */
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case SENSOR0_CORE0:
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case CORE0:
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if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0)
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sel |= AMDTEMP_TTSR_SELCORE;
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break;
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case SENSOR1_CORE1:
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sel |= AMDTEMP_TTSR_SELSENSOR;
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/* FALLTHROUGH */
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case SENSOR0_CORE1:
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case CORE1:
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if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0)
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sel |= AMDTEMP_TTSR_SELCORE;
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break;
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}
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cfg = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1);
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cfg &= ~(AMDTEMP_TTSR_SELSENSOR | AMDTEMP_TTSR_SELCORE);
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pci_write_config(dev, AMDTEMP_THERMTP_STAT, cfg | sel, 1);
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/* CurTmp starts from -49C. */
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offset = AMDTEMP_ZERO_C_TO_K - 490;
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/* Adjust offset if DiodeOffset is set and valid. */
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temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4);
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diode_offset = (temp >> 8) & 0x3f;
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if ((sc->sc_flags & AMDTEMP_FLAG_DO_ZERO) != 0) {
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if ((sc->sc_flags & AMDTEMP_FLAG_DO_SIGN) != 0 &&
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((temp >> 24) & 0x1) != 0)
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diode_offset *= -1;
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if ((sc->sc_flags & AMDTEMP_FLAG_DO_QUIRK) != 0 &&
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((temp >> 25) & 0xf) <= 2)
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diode_offset += 10;
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offset += diode_offset * 10;
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} else if (diode_offset != 0)
|
|
offset += (diode_offset - 11) * 10;
|
|
|
|
mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc;
|
|
temp = ((temp >> 14) & mask) * 5 / 2 + offset;
|
|
|
|
return (temp);
|
|
}
|
|
|
|
static int32_t
|
|
amdtemp_gettemp(device_t dev, amdsensor_t sensor)
|
|
{
|
|
uint32_t temp;
|
|
int32_t diode_offset, offset;
|
|
|
|
/* CurTmp starts from 0C. */
|
|
offset = AMDTEMP_ZERO_C_TO_K;
|
|
|
|
/* Adjust offset if DiodeOffset is set and valid. */
|
|
temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4);
|
|
diode_offset = (temp >> 8) & 0x7f;
|
|
if (diode_offset > 0 && diode_offset < 0x40)
|
|
offset += (diode_offset - 11) * 10;
|
|
|
|
temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4);
|
|
temp = ((temp >> 21) & 0x7ff) * 5 / 4 + offset;
|
|
|
|
return (temp);
|
|
}
|