73703ef8b3
> Description of fields to fill in above: 76 columns --| > PR: If a GNATS PR is affected by the change. > Submitted by: If someone else sent in the change. > Reviewed by: If someone else reviewed your modification. > Approved by: If you needed approval for this commit. > Obtained from: If the change is from a third party. > MFC after: N [day[s]|week[s]|month[s]]. Request a reminder email. > Security: Vulnerability reference (one per line) or description. > Empty fields above will be automatically removed. M rmi/xls_ehci.c M rmi/clock.h M rmi/xlr_pci.c M rmi/perfmon.h M rmi/uart_bus_xlr_iodi.c M rmi/perfmon_percpu.c M rmi/iodi.c M rmi/pcibus.c M rmi/perfmon_kern.c M rmi/perfmon_xlrconfig.h M rmi/pcibus.h M rmi/tick.c M rmi/xlr_boot1_console.c M rmi/debug.h M rmi/uart_cpu_mips_xlr.c M rmi/xlrconfig.h M rmi/interrupt.h M rmi/xlr_i2c.c M rmi/shared_structs.h M rmi/msgring.c M rmi/iomap.h M rmi/ehcireg.h M rmi/msgring.h M rmi/shared_structs_func.h M rmi/on_chip.c M rmi/pic.h M rmi/xlr_machdep.c M rmi/ehcivar.h M rmi/board.c M rmi/clock.c M rmi/shared_structs_offsets.h M rmi/perfmon_utils.h M rmi/board.h M rmi/msgring_xls.c M rmi/intr_machdep.c
164 lines
4.5 KiB
C
164 lines
4.5 KiB
C
/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RMI_BSD */
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/smp.h>
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#include <sys/sysctl.h>
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#include <machine/smp.h>
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#include <mips/rmi/perfmon.h>
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#include <mips/rmi/pic.h>
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#include <sys/mutex.h>
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#include <mips/rmi/clock.h>
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int xlr_perfmon_started = 0;
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struct perf_area *xlr_shared_config_area = NULL;
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uint32_t *xlr_perfmon_timer_loc;
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uint32_t *xlr_cpu_sampling_interval;
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uint32_t xlr_perfmon_kernel_version = 1; /* Future use */
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uint32_t xlr_perfmon_ticks;
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extern int mips_cpu_online_mask;
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extern uint32_t cpu_ltop_map[MAXCPU];
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#ifdef SMP
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static __inline__ void
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pic_send_perfmon_ipi(int cpu)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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int tid, pid;
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uint32_t ipi;
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tid = cpu & 0x3;
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pid = (cpu >> 2) & 0x7;
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ipi = (pid << 20) | (tid << 16) | IPI_PERFMON;
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mtx_lock_spin(&xlr_pic_lock);
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xlr_write_reg(mmio, PIC_IPI, ipi);
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mtx_unlock_spin(&xlr_pic_lock);
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}
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#endif
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void
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xlr_perfmon_clockhandler(void)
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{
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#ifdef SMP
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int cpu;
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int i;
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#endif
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if (xlr_perfmon_ticks++ >= (*xlr_cpu_sampling_interval) / (XLR_PIC_HZ / (hz * 1024))) {
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/* update timer */
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*xlr_perfmon_timer_loc += *xlr_cpu_sampling_interval;
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xlr_perfmon_ticks = 0;
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xlr_perfmon_sampler(NULL);
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#ifdef SMP
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for (i = 0; i < NCPUS; i = i + NTHREADS) { /* oly thread 0 */
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cpu = cpu_ltop_map[i];
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if ((mips_cpu_online_mask & (1 << i)) &&
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xlr_shared_config_area[cpu / NTHREADS].perf_config.magic ==
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PERFMON_ACTIVE_MAGIC)
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pic_send_perfmon_ipi(cpu);
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}
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#endif
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}
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}
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static void
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xlr_perfmon_start(void)
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{
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size_t size;
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size = (NCORES * sizeof(*xlr_shared_config_area)) +
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sizeof(*xlr_perfmon_timer_loc) +
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sizeof(*xlr_cpu_sampling_interval);
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xlr_shared_config_area = malloc(size, M_TEMP, M_WAITOK);
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if (!xlr_shared_config_area) {
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/* ERROR */
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return;
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}
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xlr_perfmon_timer_loc = (uint32_t *) (xlr_shared_config_area + NCORES);
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xlr_cpu_sampling_interval = (uint32_t *) (xlr_perfmon_timer_loc + 1);
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*xlr_cpu_sampling_interval = DEFAULT_CPU_SAMPLING_INTERVAL;
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*xlr_perfmon_timer_loc = 0;
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xlr_perfmon_ticks = 0;
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xlr_perfmon_init_cpu(NULL);
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#ifdef SMP
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smp_call_function(xlr_perfmon_init_cpu, NULL,
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PCPU_GET(other_cpus) & 0x11111111);
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#endif
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xlr_perfmon_started = 1;
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}
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static void
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xlr_perfmon_stop(void)
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{
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xlr_perfmon_started = 0;
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free(xlr_shared_config_area, M_TEMP);
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xlr_shared_config_area = NULL;
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}
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static int
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sysctl_xlr_perfmon_start_stop(SYSCTL_HANDLER_ARGS)
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{
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int error, val = xlr_perfmon_started;
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error = sysctl_handle_int(oidp, &val, 0, req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (!xlr_perfmon_started && val != 0)
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xlr_perfmon_start();
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else if (xlr_perfmon_started && val == 0)
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xlr_perfmon_stop();
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return (0);
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}
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SYSCTL_NODE(_debug, OID_AUTO, xlrperf, CTLFLAG_RW, NULL, "XLR PERF Nodes");
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SYSCTL_PROC(_debug_xlrperf, OID_AUTO, start, CTLTYPE_INT | CTLFLAG_RW,
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&xlr_perfmon_started, 0, sysctl_xlr_perfmon_start_stop, "I", "set/unset to start/stop "
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"performance monitoring");
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