75 lines
3.9 KiB
C
75 lines
3.9 KiB
C
/*-
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* Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define AICFR 0x00 /* AIC Configuration Register */
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#define AICFR_TFTH_S 16 /* Transmit FIFO threshold for interrupt or DMA request. */
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#define AICFR_TFTH_M (0x1f << AICFR_TFTH_S)
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#define AICFR_TFTH(x) ((x) << AICFR_TFTH_S)
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#define AICFR_RFTH_S 24 /* Receive FIFO threshold for interrupt or DMA request. */
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#define AICFR_RFTH_M (0x0f << AICFR_RFTH_S)
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#define AICFR_RFTH(x) ((x) << AICFR_RFTH_S)
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#define AICFR_ICDC (1 << 5) /* Internal CODEC used. */
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#define AICFR_AUSEL (1 << 4) /* Audio Unit Select */
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#define AICFR_RST (1 << 3) /* Reset AIC. */
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#define AICFR_BCKD (1 << 2) /* BIT_CLK Direction. */
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#define AICFR_SYNCD (1 << 1) /* SYNC is generated internally and driven out to the CODEC. */
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#define AICFR_ENB (1 << 0) /* Enable AIC Controller. */
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#define AICCR 0x04 /* AIC Common Control Register */
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#define AICCR_TFLUSH (1 << 8) /* Transmit FIFO Flush. */
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#define AICCR_RFLUSH (1 << 7) /* Receive FIFO Flush. */
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#define AICCR_CHANNEL_S 24
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#define AICCR_CHANNEL_M (0x7 << AICCR_CHANNEL_S)
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#define AICCR_CHANNEL_2 (0x1 << AICCR_CHANNEL_S) /* 2 channels, stereo */
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#define AICCR_ISS_S 16 /* Input Sample Size. */
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#define AICCR_ISS_M (0x7 << AICCR_ISS_S)
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#define AICCR_ISS_16 (0x1 << AICCR_ISS_S)
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#define AICCR_OSS_S 19 /* Output Sample Size. */
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#define AICCR_OSS_M (0x7 << AICCR_OSS_S)
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#define AICCR_OSS_16 (0x1 << AICCR_OSS_S)
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#define AICCR_RDMS (1 << 15) /* Receive DMA enable. */
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#define AICCR_TDMS (1 << 14) /* Transmit DMA enable. */
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#define AICCR_ENLBF (1 << 2) /* Enable AIC Loop Back Function. */
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#define AICCR_ERPL (1 << 1) /* Enable Playing Back function. */
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#define I2SCR 0x10 /* AIC I2S/MSB-justified Control */
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#define I2SCR_ESCLK (1 << 4) /* Enable SYSCLK output. */
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#define I2SCR_AMSL (1 << 0) /* Select MSB-Justified Operation Mode. */
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#define AICSR 0x14 /* AIC FIFO Status Register Register */
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#define I2SSR 0x1C /* AIC I2S/MSB-justified Status Register */
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#define I2SDIV 0x30 /* AIC I2S/MSB-justified Clock Divider Register */
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#define AICDR 0x34 /* AIC FIFO Data Port Register */
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#define SPENA 0x80 /* SPDIF Enable Register */
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#define SPCTRL 0x84 /* SPDIF Control Register */
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#define SPSTATE 0x88 /* SPDIF Status Register */
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#define SPCFG1 0x8C /* SPDIF Configure 1 Register */
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#define SPCFG2 0x90 /* SPDIF Configure 2 Register */
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#define SPFIFO 0x94 /* SPDIF FIFO Register */
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