e8a9ef1b0e
bhyve uses cached copies of the MSI capability registers to generate MSI interrupts for device models. Previously, these cached fields were only set when the MSI capability control register was updated. The Linux kernel recently adopted a change to deal with races in MSI interrupt delivery that writes to the MSI capability address and data registers to alter the destination of MSI interrupts without writing to the MSI capability control register. bhyve was not updating its cached registers for these writes and continued to send interrupts with the old data value to the old address. Fix this by recomputing the cached values for every write to any MSI capability register. Reported by: Jason Tubnor, Ryan Moeller Reported by: Marc Dionne (bisected the Linux kernel commit) Reviewed by: grehan MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D24593
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