7d12b6e172
As with the AR9285, the AR9287 has a default word of 0x1F which means all the various bits in that field are set on by default.
478 lines
15 KiB
C
478 lines
15 KiB
C
/*
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* Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_devid.h"
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#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */
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#include "ah_eeprom_9287.h"
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#include "ar9002/ar9280.h"
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#include "ar9002/ar9287.h"
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#include "ar5416/ar5416reg.h"
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#include "ar5416/ar5416phy.h"
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#include "ar9002/ar9287_cal.h"
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#include "ar9002/ar9287_reset.h"
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#include "ar9002/ar9287_olc.h"
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#include "ar9002/ar9287.ini"
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static const HAL_PERCAL_DATA ar9287_iq_cal = { /* single sample */
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.calName = "IQ", .calType = IQ_MISMATCH_CAL,
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.calNumSamples = MIN_CAL_SAMPLES,
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.calCountMax = PER_MAX_LOG_COUNT,
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.calCollect = ar5416IQCalCollect,
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.calPostProc = ar5416IQCalibration
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};
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static const HAL_PERCAL_DATA ar9287_adc_gain_cal = { /* single sample */
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.calName = "ADC Gain", .calType = ADC_GAIN_CAL,
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.calNumSamples = MIN_CAL_SAMPLES,
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.calCountMax = PER_MIN_LOG_COUNT,
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.calCollect = ar5416AdcGainCalCollect,
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.calPostProc = ar5416AdcGainCalibration
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};
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static const HAL_PERCAL_DATA ar9287_adc_dc_cal = { /* single sample */
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.calName = "ADC DC", .calType = ADC_DC_CAL,
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.calNumSamples = MIN_CAL_SAMPLES,
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.calCountMax = PER_MIN_LOG_COUNT,
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.calCollect = ar5416AdcDcCalCollect,
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.calPostProc = ar5416AdcDcCalibration
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};
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static const HAL_PERCAL_DATA ar9287_adc_init_dc_cal = {
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.calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
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.calNumSamples = MIN_CAL_SAMPLES,
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.calCountMax = INIT_LOG_COUNT,
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.calCollect = ar5416AdcDcCalCollect,
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.calPostProc = ar5416AdcDcCalibration
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};
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static void ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
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static HAL_BOOL ar9287FillCapabilityInfo(struct ath_hal *ah);
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static void ar9287WriteIni(struct ath_hal *ah,
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const struct ieee80211_channel *chan);
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static void
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ar9287AniSetup(struct ath_hal *ah)
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{
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/*
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* These are the parameters from the AR5416 ANI code;
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* they likely need quite a bit of adjustment for the
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* AR9280.
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*/
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static const struct ar5212AniParams aniparams = {
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.maxNoiseImmunityLevel = 4, /* levels 0..4 */
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.totalSizeDesired = { -55, -55, -55, -55, -62 },
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.coarseHigh = { -14, -14, -14, -14, -12 },
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.coarseLow = { -64, -64, -64, -64, -70 },
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.firpwr = { -78, -78, -78, -78, -80 },
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.maxSpurImmunityLevel = 2,
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.cycPwrThr1 = { 2, 4, 6 },
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.maxFirstepLevel = 2, /* levels 0..2 */
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.firstep = { 0, 4, 8 },
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.ofdmTrigHigh = 500,
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.ofdmTrigLow = 200,
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.cckTrigHigh = 200,
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.cckTrigLow = 100,
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.rssiThrHigh = 40,
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.rssiThrLow = 7,
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.period = 100,
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};
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/* NB: disable ANI noise immmunity for reliable RIFS rx */
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AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL;
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/* NB: ANI is not enabled yet */
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ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
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}
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/*
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* Attach for an AR9287 part.
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*/
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static struct ath_hal *
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ar9287Attach(uint16_t devid, HAL_SOFTC sc,
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HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
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HAL_STATUS *status)
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{
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struct ath_hal_9287 *ahp9287;
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struct ath_hal_5212 *ahp;
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struct ath_hal *ah;
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uint32_t val;
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HAL_STATUS ecode;
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HAL_BOOL rfStatus;
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int8_t pwr_table_offset;
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HALDEBUG_G(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
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__func__, sc, (void*) st, (void*) sh);
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/* NB: memory is returned zero'd */
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ahp9287 = ath_hal_malloc(sizeof (struct ath_hal_9287));
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if (ahp9287 == AH_NULL) {
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HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY,
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"%s: cannot allocate memory for state block\n", __func__);
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*status = HAL_ENOMEM;
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return AH_NULL;
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}
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ahp = AH5212(ahp9287);
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ah = &ahp->ah_priv.h;
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ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
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/* XXX override with 9280 specific state */
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/* override 5416 methods for our needs */
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ah->ah_setAntennaSwitch = ar9287SetAntennaSwitch;
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ah->ah_configPCIE = ar9287ConfigPCIE;
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AH5416(ah)->ah_cal.iqCalData.calData = &ar9287_iq_cal;
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AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9287_adc_gain_cal;
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AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9287_adc_dc_cal;
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AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9287_adc_init_dc_cal;
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/* Better performance without ADC Gain Calibration */
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AH5416(ah)->ah_cal.suppCals = ADC_DC_CAL | IQ_MISMATCH_CAL;
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AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
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AH5416(ah)->ah_writeIni = ar9287WriteIni;
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ah->ah_setTxPower = ar9287SetTransmitPower;
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ah->ah_setBoardValues = ar9287SetBoardValues;
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AH5416(ah)->ah_olcInit = ar9287olcInit;
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AH5416(ah)->ah_olcTempCompensation = ar9287olcTemperatureCompensation;
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//AH5416(ah)->ah_setPowerCalTable = ar9287SetPowerCalTable;
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AH5416(ah)->ah_cal_initcal = ar9287InitCalHardware;
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AH5416(ah)->ah_cal_pacal = ar9287PACal;
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/* XXX NF calibration */
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/* XXX Ini override? (IFS vars - since the kiwi mac clock is faster?) */
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/* XXX what else is kiwi-specific in the radio/calibration pathway? */
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AH5416(ah)->ah_rx_chainmask = AR9287_DEFAULT_RXCHAINMASK;
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AH5416(ah)->ah_tx_chainmask = AR9287_DEFAULT_TXCHAINMASK;
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if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
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/* reset chip */
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
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__func__);
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ecode = HAL_EIO;
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goto bad;
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}
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if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
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__func__);
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ecode = HAL_EIO;
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goto bad;
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}
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/* Read Revisions from Chips before taking out of reset */
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val = OS_REG_READ(ah, AR_SREV);
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HALDEBUG(ah, HAL_DEBUG_ATTACH,
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"%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
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__func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
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MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
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/* NB: include chip type to differentiate from pre-Sowl versions */
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AH_PRIVATE(ah)->ah_macVersion =
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(val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
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AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
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AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
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/* Don't support Kiwi < 1.2; those are pre-release chips */
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if (! AR_SREV_KIWI_12_OR_LATER(ah)) {
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ath_hal_printf(ah, "[ath]: Kiwi < 1.2 is not supported\n");
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ecode = HAL_EIO;
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goto bad;
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}
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/* setup common ini data; rf backends handle remainder */
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HAL_INI_INIT(&ahp->ah_ini_modes, ar9287Modes_9287_1_1, 6);
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HAL_INI_INIT(&ahp->ah_ini_common, ar9287Common_9287_1_1, 2);
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/* If pcie_clock_req */
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HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
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ar9287PciePhy_clkreq_always_on_L1_9287_1_1, 2);
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/* XXX WoW ini values */
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/* Else */
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#if 0
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HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
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ar9287PciePhy_clkreq_off_L1_9287_1_1, 2);
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#endif
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/* Initialise Japan arrays */
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HAL_INI_INIT(&ahp9287->ah_ini_cckFirNormal,
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ar9287Common_normal_cck_fir_coeff_9287_1_1, 2);
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HAL_INI_INIT(&ahp9287->ah_ini_cckFirJapan2484,
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ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, 2);
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ar5416AttachPCIE(ah);
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ecode = ath_hal_9287EepromAttach(ah);
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if (ecode != HAL_OK)
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goto bad;
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if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
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ecode = HAL_EIO;
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goto bad;
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}
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AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
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if (!ar5212ChipTest(ah)) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
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__func__);
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ecode = HAL_ESELFTEST;
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goto bad;
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}
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/*
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* Set correct Baseband to analog shift
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* setting to access analog chips.
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*/
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OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
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/* Read Radio Chip Rev Extract */
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AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
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switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
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case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
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case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
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break;
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default:
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if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
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AH_PRIVATE(ah)->ah_analog5GhzRev =
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AR_RAD5133_SREV_MAJOR;
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break;
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}
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#ifdef AH_DEBUG
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: 5G Radio Chip Rev 0x%02X is not supported by "
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"this driver\n", __func__,
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AH_PRIVATE(ah)->ah_analog5GhzRev);
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ecode = HAL_ENOTSUPP;
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goto bad;
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#endif
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}
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rfStatus = ar9287RfAttach(ah, &ecode);
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if (!rfStatus) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
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__func__, ecode);
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goto bad;
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}
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/*
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* We only implement open-loop TX power control
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* for the AR9287 in this codebase.
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*/
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if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
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ath_hal_printf(ah, "[ath] AR9287 w/ closed-loop TX power control"
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" isn't supported.\n");
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ecode = HAL_ENOTSUPP;
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goto bad;
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}
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/*
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* Check whether the power table offset isn't the default.
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* This can occur with eeprom minor V21 or greater on Merlin.
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*/
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(void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset);
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if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB)
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ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n",
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AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset);
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/* setup rxgain table */
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HAL_INI_INIT(&ahp9287->ah_ini_rxgain, ar9287Modes_rx_gain_9287_1_1, 6);
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/* setup txgain table */
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HAL_INI_INIT(&ahp9287->ah_ini_txgain, ar9287Modes_tx_gain_9287_1_1, 6);
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/*
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* Got everything we need now to setup the capabilities.
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*/
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if (!ar9287FillCapabilityInfo(ah)) {
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ecode = HAL_EEREAD;
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goto bad;
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}
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ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
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if (ecode != HAL_OK) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: error getting mac address from EEPROM\n", __func__);
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goto bad;
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}
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/* XXX How about the serial number ? */
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/* Read Reg Domain */
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AH_PRIVATE(ah)->ah_currentRD =
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ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
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AH_PRIVATE(ah)->ah_currentRDext = AR9287_RDEXT_DEFAULT;
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/*
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* ah_miscMode is populated by ar5416FillCapabilityInfo()
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* starting from griffin. Set here to make sure that
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* AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
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* placed into hardware.
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*/
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if (ahp->ah_miscMode != 0)
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OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
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ar9287AniSetup(ah); /* Anti Noise Immunity */
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/* Setup noise floor min/max/nominal values */
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AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
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AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
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AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
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AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_5GHZ;
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AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_5GHZ;
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AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9287_5GHZ;
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ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
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HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
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return ah;
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bad:
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if (ah != AH_NULL)
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ah->ah_detach(ah);
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if (status)
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*status = ecode;
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return AH_NULL;
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}
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static void
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ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
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{
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if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
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ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
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OS_DELAY(1000);
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OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
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OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); /* Yes, Kiwi uses the Kite PCIe PHY WA */
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}
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}
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static void
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ar9287WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
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{
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u_int modesIndex, freqIndex;
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int regWrites = 0;
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/* Setup the indices for the next set of register array writes */
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/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
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if (IEEE80211_IS_CHAN_2GHZ(chan)) {
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freqIndex = 2;
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if (IEEE80211_IS_CHAN_HT40(chan))
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modesIndex = 3;
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else if (IEEE80211_IS_CHAN_108G(chan))
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modesIndex = 5;
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else
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modesIndex = 4;
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} else {
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freqIndex = 1;
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if (IEEE80211_IS_CHAN_HT40(chan) ||
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IEEE80211_IS_CHAN_TURBO(chan))
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modesIndex = 2;
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else
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modesIndex = 1;
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}
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/* Set correct Baseband to analog shift setting to access analog chips. */
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OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
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OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
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regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, modesIndex, regWrites);
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regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_rxgain, modesIndex, regWrites);
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regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_txgain, modesIndex, regWrites);
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regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 1, regWrites);
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}
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#define AR_BASE_FREQ_2GHZ 2300
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#define AR_BASE_FREQ_5GHZ 4900
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#define AR_SPUR_FEEQ_BOUND_HT40 19
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#define AR_SPUR_FEEQ_BOUND_HT20 10
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/*
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* Fill all software cached or static hardware state information.
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* Return failure if capabilities are to come from EEPROM and
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* cannot be read.
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*/
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static HAL_BOOL
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ar9287FillCapabilityInfo(struct ath_hal *ah)
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{
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HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
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if (!ar5416FillCapabilityInfo(ah))
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return AH_FALSE;
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pCap->halNumGpioPins = 10;
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|
pCap->halWowSupport = AH_TRUE;
|
|
pCap->halWowMatchPatternExact = AH_TRUE;
|
|
#if 0
|
|
pCap->halWowMatchPatternDword = AH_TRUE;
|
|
#endif
|
|
|
|
pCap->halCSTSupport = AH_TRUE;
|
|
pCap->halRifsRxSupport = AH_TRUE;
|
|
pCap->halRifsTxSupport = AH_TRUE;
|
|
pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
|
|
pCap->halExtChanDfsSupport = AH_TRUE;
|
|
pCap->halUseCombinedRadarRssi = AH_TRUE;
|
|
#if 0
|
|
/* XXX bluetooth */
|
|
pCap->halBtCoexSupport = AH_TRUE;
|
|
#endif
|
|
pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
|
|
pCap->hal4kbSplitTransSupport = AH_FALSE;
|
|
/* Disable this so Block-ACK works correctly */
|
|
pCap->halHasRxSelfLinkedTail = AH_FALSE;
|
|
pCap->halPSPollBroken = AH_FALSE;
|
|
|
|
/* Hardware supports (at least) single-stream STBC TX/RX */
|
|
pCap->halRxStbcSupport = 1;
|
|
pCap->halTxStbcSupport = 1;
|
|
|
|
/* Hardware supports short-GI w/ 20MHz */
|
|
pCap->halHTSGI20Support = 1;
|
|
|
|
pCap->halEnhancedDfsSupport = AH_TRUE;
|
|
|
|
return AH_TRUE;
|
|
}
|
|
|
|
/*
|
|
* This has been disabled - having the HAL flip chainmasks on/off
|
|
* when attempting to implement 11n disrupts things. For now, just
|
|
* leave this flipped off and worry about implementing TX diversity
|
|
* for legacy and MCS0-7 when 11n is fully functioning.
|
|
*/
|
|
HAL_BOOL
|
|
ar9287SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
|
|
{
|
|
return AH_TRUE;
|
|
}
|
|
|
|
static const char*
|
|
ar9287Probe(uint16_t vendorid, uint16_t devid)
|
|
{
|
|
if (vendorid == ATHEROS_VENDOR_ID &&
|
|
(devid == AR9287_DEVID_PCI || devid == AR9287_DEVID_PCIE))
|
|
return "Atheros 9287";
|
|
return AH_NULL;
|
|
}
|
|
AH_CHIP(AR9287, ar9287Probe, ar9287Attach);
|