272 lines
7.6 KiB
C
272 lines
7.6 KiB
C
/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* DWC3 USB 3.0 DRD (dual role device) PHY
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <sys/gpio.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <arm/samsung/exynos/exynos5_common.h>
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#include <arm/samsung/exynos/exynos5_pmu.h>
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#include "gpio_if.h"
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#define USB_DRD_LINKSYSTEM 0x04
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#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
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#define LINKSYSTEM_FLADJ(x) ((x) << 1)
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#define LINKSYSTEM_XHCI_VERSION_CTRL (1 << 27)
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#define USB_DRD_PHYUTMI 0x08
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#define PHYUTMI_OTGDISABLE (1 << 6)
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#define PHYUTMI_FORCESUSPEND (1 << 1)
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#define PHYUTMI_FORCESLEEP (1 << 0)
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#define USB_DRD_PHYPIPE 0x0c
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#define USB_DRD_PHYCLKRST 0x10
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#define PHYCLKRST_PORTRESET (1 << 1)
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#define PHYCLKRST_COMMONONN (1 << 0)
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#define PHYCLKRST_EN_UTMISUSPEND (1 << 31)
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#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
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#define PHYCLKRST_SSC_REFCLKSEL(x) ((x) << 23)
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#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
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#define PHYCLKRST_SSC_RANGE(x) ((x) << 21)
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#define PHYCLKRST_SSC_EN (1 << 20)
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#define PHYCLKRST_REF_SSP_EN (1 << 19)
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#define PHYCLKRST_REF_CLKDIV2 (1 << 18)
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#define PHYCLKRST_MPLL_MLTPR_MASK (0x7f << 11)
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#define PHYCLKRST_MPLL_MLTPR_100MHZ (0x19 << 11)
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#define PHYCLKRST_MPLL_MLTPR_50M (0x32 << 11)
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#define PHYCLKRST_MPLL_MLTPR_24MHZ (0x68 << 11)
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#define PHYCLKRST_MPLL_MLTPR_20MHZ (0x7d << 11)
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#define PHYCLKRST_MPLL_MLTPR_19200KHZ (0x02 << 11)
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#define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5)
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#define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8)
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#define PHYCLKRST_FSEL(x) ((x) << 5)
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#define PHYCLKRST_FSEL_9MHZ6 0x0
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#define PHYCLKRST_FSEL_10MHZ 0x1
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#define PHYCLKRST_FSEL_12MHZ 0x2
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#define PHYCLKRST_FSEL_19MHZ2 0x3
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#define PHYCLKRST_FSEL_20MHZ 0x4
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#define PHYCLKRST_FSEL_24MHZ 0x5
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#define PHYCLKRST_FSEL_50MHZ 0x7
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#define PHYCLKRST_RETENABLEN (1 << 4)
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#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
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#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
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#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
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#define USB_DRD_PHYREG0 0x14
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#define USB_DRD_PHYREG1 0x18
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#define USB_DRD_PHYPARAM0 0x1c
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#define PHYPARAM0_REF_USE_PAD (1 << 31)
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#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
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#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
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#define USB_DRD_PHYPARAM1 0x20
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#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
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#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
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#define USB_DRD_PHYTERM 0x24
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#define USB_DRD_PHYTEST 0x28
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#define PHYTEST_POWERDOWN_SSP (1 << 3)
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#define PHYTEST_POWERDOWN_HSP (1 << 2)
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#define USB_DRD_PHYADP 0x2c
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#define USB_DRD_PHYUTMICLKSEL 0x30
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#define PHYUTMICLKSEL_UTMI_CLKSEL (1 << 2)
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#define USB_DRD_PHYRESUME 0x34
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#define USB_DRD_LINKPORT 0x44
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struct usb_phy_softc {
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struct resource *res[1];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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device_t dev;
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};
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static struct resource_spec usb_phy_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int
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usb_phy_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "samsung,exynos5420-usbdrd-phy"))
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return (ENXIO);
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device_set_desc(dev, "Samsung Exynos 5 USB PHY");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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vbus_on(struct usb_phy_softc *sc)
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{
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pcell_t dts_value[3];
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device_t gpio_dev;
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phandle_t node;
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pcell_t pin;
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int len;
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if ((node = ofw_bus_get_node(sc->dev)) == -1)
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return (-1);
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/* Power pin */
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if ((len = OF_getproplen(node, "vbus-supply")) <= 0)
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return (-1);
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OF_getencprop(node, "vbus-supply", dts_value, len);
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pin = dts_value[0];
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gpio_dev = devclass_get_device(devclass_find("gpio"), 0);
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if (gpio_dev == NULL) {
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device_printf(sc->dev, "can't find gpio_dev\n");
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return (1);
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}
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GPIO_PIN_SETFLAGS(gpio_dev, pin, GPIO_PIN_OUTPUT);
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GPIO_PIN_SET(gpio_dev, pin, GPIO_PIN_HIGH);
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return (0);
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}
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static int
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usb3_phy_init(struct usb_phy_softc *sc)
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{
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int reg;
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/* Reset USB 3.0 PHY */
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WRITE4(sc, USB_DRD_PHYREG0, 0);
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reg = READ4(sc, USB_DRD_PHYPARAM0);
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/* PHY CLK src */
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reg &= ~(PHYPARAM0_REF_USE_PAD);
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reg &= ~(PHYPARAM0_REF_LOSLEVEL_MASK);
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reg |= (PHYPARAM0_REF_LOSLEVEL);
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WRITE4(sc, USB_DRD_PHYPARAM0, reg);
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WRITE4(sc, USB_DRD_PHYRESUME, 0);
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reg = (LINKSYSTEM_XHCI_VERSION_CTRL |
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LINKSYSTEM_FLADJ(0x20));
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WRITE4(sc, USB_DRD_LINKSYSTEM, reg);
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reg = READ4(sc, USB_DRD_PHYPARAM1);
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reg &= ~(PHYPARAM1_PCS_TXDEEMPH_MASK);
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reg |= (PHYPARAM1_PCS_TXDEEMPH);
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WRITE4(sc, USB_DRD_PHYPARAM1, reg);
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reg = READ4(sc, USB_DRD_PHYUTMICLKSEL);
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reg |= (PHYUTMICLKSEL_UTMI_CLKSEL);
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WRITE4(sc, USB_DRD_PHYUTMICLKSEL, reg);
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reg = READ4(sc, USB_DRD_PHYTEST);
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reg &= ~(PHYTEST_POWERDOWN_HSP);
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reg &= ~(PHYTEST_POWERDOWN_SSP);
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WRITE4(sc, USB_DRD_PHYTEST, reg);
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WRITE4(sc, USB_DRD_PHYUTMI, PHYUTMI_OTGDISABLE);
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/* Clock */
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reg = (PHYCLKRST_REFCLKSEL_EXT_REFCLK);
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reg |= (PHYCLKRST_FSEL(PHYCLKRST_FSEL_24MHZ));
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reg |= (PHYCLKRST_MPLL_MLTPR_24MHZ);
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reg |= (PHYCLKRST_SSC_REFCLKSEL(0x88));
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reg |= (PHYCLKRST_RETENABLEN |
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PHYCLKRST_REF_SSP_EN | /* Super speed */
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PHYCLKRST_SSC_EN | /* Spread spectrum */
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PHYCLKRST_COMMONONN |
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PHYCLKRST_PORTRESET);
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WRITE4(sc, USB_DRD_PHYCLKRST, reg);
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DELAY(50000);
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reg &= ~PHYCLKRST_PORTRESET;
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WRITE4(sc, USB_DRD_PHYCLKRST, reg);
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return (0);
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}
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static int
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usb_phy_attach(device_t dev)
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{
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struct usb_phy_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, usb_phy_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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/* Memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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vbus_on(sc);
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usbdrd_phy_power_on();
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DELAY(100);
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usb3_phy_init(sc);
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return (0);
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}
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static device_method_t usb_phy_methods[] = {
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DEVMETHOD(device_probe, usb_phy_probe),
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DEVMETHOD(device_attach, usb_phy_attach),
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{ 0, 0 }
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};
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static driver_t usb_phy_driver = {
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"usb_phy",
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usb_phy_methods,
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sizeof(struct usb_phy_softc),
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};
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static devclass_t usb_phy_devclass;
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DRIVER_MODULE(usb_phy, simplebus, usb_phy_driver, usb_phy_devclass, 0, 0);
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