263 lines
6.4 KiB
Plaintext
263 lines
6.4 KiB
Plaintext
/*-
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* Copyright (c) 2012-2013 Robert N. M. Watson
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* Copyright (c) 2013 SRI International
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/dts-v1/;
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/*
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* Device names here have been largely made up on the spot, especially for the
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* "compatible" strings, and might want to be revised.
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*
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* For now, use 32-bit addressing as our Avalon bus is 32-bit. However, in
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* the future, we should likely change to 64-bit.
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*/
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/ {
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model = "SRI/Cambridge BeriPad (DE4)";
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compatible = "sri-cambridge,beripad-de4";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* Secondary CPUs all start disabled and use the
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* spin-table enable method. cpu-release-addr must be
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* specified for each cpu other than cpu@0. Values of
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* cpu-release-addr grow down from 0x100000 (kernel).
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*/
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status = "disabled";
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enable-method = "spin-table";
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cpu@0 {
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device-type = "cpu";
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compatible = "sri-cambridge,beri";
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reg = <0 1>;
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status = "okay";
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};
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/*
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cpu@1 {
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device-type = "cpu";
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compatible = "sri-cambridge,beri";
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reg = <1 1>;
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// XXX: should we need cached prefix?
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cpu-release-addr = <0xffffffff 0x800fffe0>;
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};
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*/
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x40000000>; // 1G at 0x0
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};
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cpuintc: cpuintc@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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beripic0: beripic@7f804000 {
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compatible = "sri-cambridge,beri-pic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x7f804000 0x400
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0x7f806000 0x10
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0x7f806080 0x10
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0x7f806100 0x10>;
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interrupts = < 2 3 4 5 6 >;
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hard-interrupt-sources = <64>;
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soft-interrupt-sources = <64>;
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interrupt-parent = <&cpuintc>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <1>;
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compatible = "simple-bus", "mips,mips4k";
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ranges;
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serial@7f002100 {
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compatible = "ns16550";
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reg = <0x7f002100 0x20>;
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reg-shift = <2>;
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clock-frequency = <50000000>;
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interrupts = <6>;
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interrupt-parent = <&beripic0>;
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};
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serial@7f000000 {
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compatible = "altera,jtag_uart-11_0";
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reg = <0x7f000000 0x40>;
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interrupts = <0>;
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interrupt-parent = <&beripic0>;
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};
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serial@7f001000 {
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compatible = "altera,jtag_uart-11_0";
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reg = <0x7f001000 0x40>;
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};
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serial@7f002000 {
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compatible = "altera,jtag_uart-11_0";
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reg = <0x7f002000 0x40>;
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};
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sdcard@7f008000 {
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compatible = "altera,sdcard_11_2011";
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reg = <0x7f008000 0x400>;
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};
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led@7f006000 {
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compatible = "sri-cambridge,de4led";
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reg = <0x7f006000 0x1>;
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};
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/*
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* XXX-BZ keep flash before ethernet so that atse can read the
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* Ethernet addresses for now.
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*/
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flash@74000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x74000000 0x4000000>;
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/* Board configuration */
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partition@0 {
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reg = <0x0 0x20000>;
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label = "config";
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};
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/* Power up FPGA image */
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partition@20000 {
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reg = <0x20000 0xc00000>;
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label = "fpga0";
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};
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/* Secondary FPGA image (on RE_CONFIGn button) */
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partition@C20000 {
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reg = <0xc20000 0xc00000>;
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label = "fpga1";
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};
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/* Space for operating system use */
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partition@1820000 {
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reg = <0x1820000 0x027c0000>;
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label = "os";
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};
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/* Second stage bootloader */
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parition@3fe0000 {
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reg = <0x3fe0000 0x20000>;
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label = "boot";
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};
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};
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ethernet@7f007000 {
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compatible = "altera,atse";
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// MAC, RX+RXC, TX+TXC.
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reg = <0x7f007000 0x400
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0x7f007500 0x8
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0x7f007520 0x20
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0x7f007400 0x8
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0x7f007420 0x20>;
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// RX, TX
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interrupts = <1 2>;
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interrupt-parent = <&beripic0>;
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};
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ethernet@7f005000 {
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compatible = "altera,atse";
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// MAC, RX+RXC, TX+TXC.
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reg = <0x7f005000 0x400
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0x7f005500 0x8
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0x7f005520 0x20
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0x7f005400 0x8
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0x7f005420 0x20>;
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// RX, TX
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interrupts = <11 12>;
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interrupt-parent = <&beripic0>;
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};
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touchscreen@70400000 {
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compatible = "sri-cambridge,mtl";
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panel-size = < 800 480 >;
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reg = <0x70400000 0x1000
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0x70000000 0x177000
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0x70177000 0x2000>;
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};
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usb@0x7f100000 {
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compatible = "nxp,usb-isp1761";
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reg = <0x7f100000 0x40000
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0x7f140000 0x4>;
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// IRQ 4 is DC, IRQ 5 is HC.
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interrupts = <4 5>;
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interrupt-parent = <&beripic0>;
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};
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avgen@0x7f009000 {
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compatible = "sri-cambridge,avgen";
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reg = <0x7f009000 0x2>;
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sri-cambridge,width = <1>;
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sri-cambridge,fileio = "r";
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sri-cambridge,devname = "de4bsw";
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};
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avgen@0x7f00a000 {
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compatible = "sri-cambridge,avgen";
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reg = <0x7f00a000 0x14>;
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sri-cambridge,width = <4>;
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sri-cambridge,fileio = "rw";
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sri-cambridge,devname = "berirom";
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};
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avgen@0x7f00c000 {
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compatible = "sri-cambridge,avgen";
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reg = <0x7f00c000 0x8>;
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sri-cambridge,width = <4>;
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sri-cambridge,fileio = "rw";
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sri-cambridge,devname = "de4tempfan";
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};
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};
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};
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