37ea599bf7
Follow up r319935 by actually committing the mpc85xx_get_platform_clock() function. This function was created to facilitate other development, and I thought I had committed it earlier. Some blocks depend on the platform clock rather than the system clock. The System clock is derived from the platform clock as one-half the platform clock. Rewrite mpc85xx_get_system_clock() to use the new function. Pointy-hat to: jhibbits
466 lines
9.7 KiB
C
466 lines
9.7 KiB
C
/*-
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* Copyright (C) 2008 Semihalf, Rafal Jaworowski
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/reboot.h>
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#include <sys/rman.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/machdep.h>
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#include <machine/pio.h>
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#include <machine/spr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/openfirm.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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/*
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* MPC85xx system specific routines
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*/
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uint32_t
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ccsr_read4(uintptr_t addr)
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{
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volatile uint32_t *ptr = (void *)addr;
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return (*ptr);
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}
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void
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ccsr_write4(uintptr_t addr, uint32_t val)
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{
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volatile uint32_t *ptr = (void *)addr;
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*ptr = val;
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powerpc_iomb();
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}
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int
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law_getmax(void)
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{
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uint32_t ver;
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int law_max;
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ver = SVR_VER(mfspr(SPR_SVR));
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switch (ver) {
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case SVR_MPC8555:
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case SVR_MPC8555E:
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law_max = 8;
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break;
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case SVR_MPC8533:
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case SVR_MPC8533E:
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case SVR_MPC8548:
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case SVR_MPC8548E:
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law_max = 10;
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break;
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case SVR_P5020:
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case SVR_P5020E:
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law_max = 32;
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break;
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default:
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law_max = 8;
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}
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return (law_max);
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}
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static inline void
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law_write(uint32_t n, uint64_t bar, uint32_t sr)
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{
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if (mpc85xx_is_qoriq()) {
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ccsr_write4(OCP85XX_LAWBARH(n), bar >> 32);
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ccsr_write4(OCP85XX_LAWBARL(n), bar);
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ccsr_write4(OCP85XX_LAWSR_QORIQ(n), sr);
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ccsr_read4(OCP85XX_LAWSR_QORIQ(n));
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} else {
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ccsr_write4(OCP85XX_LAWBAR(n), bar >> 12);
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ccsr_write4(OCP85XX_LAWSR_85XX(n), sr);
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ccsr_read4(OCP85XX_LAWSR_85XX(n));
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}
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/*
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* The last write to LAWAR should be followed by a read
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* of LAWAR before any device try to use any of windows.
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* What more the read of LAWAR should be followed by isync
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* instruction.
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*/
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isync();
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}
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static inline void
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law_read(uint32_t n, uint64_t *bar, uint32_t *sr)
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{
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if (mpc85xx_is_qoriq()) {
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*bar = (uint64_t)ccsr_read4(OCP85XX_LAWBARH(n)) << 32 |
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ccsr_read4(OCP85XX_LAWBARL(n));
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*sr = ccsr_read4(OCP85XX_LAWSR_QORIQ(n));
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} else {
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*bar = (uint64_t)ccsr_read4(OCP85XX_LAWBAR(n)) << 12;
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*sr = ccsr_read4(OCP85XX_LAWSR_85XX(n));
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}
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}
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static int
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law_find_free(void)
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{
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uint32_t i,sr;
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uint64_t bar;
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int law_max;
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law_max = law_getmax();
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/* Find free LAW */
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for (i = 0; i < law_max; i++) {
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law_read(i, &bar, &sr);
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if ((sr & 0x80000000) == 0)
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break;
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}
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return (i);
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}
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#define _LAW_SR(trgt,size) (0x80000000 | (trgt << 20) | \
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(flsl(size + (size - 1)) - 2))
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int
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law_enable(int trgt, uint64_t bar, uint32_t size)
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{
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uint64_t bar_tmp;
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uint32_t sr, sr_tmp;
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int i, law_max;
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if (size == 0)
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return (0);
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law_max = law_getmax();
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sr = _LAW_SR(trgt, size);
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/* Bail if already programmed. */
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for (i = 0; i < law_max; i++) {
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law_read(i, &bar_tmp, &sr_tmp);
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if (sr == sr_tmp && bar == bar_tmp)
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return (0);
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}
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/* Find an unused access window. */
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i = law_find_free();
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if (i == law_max)
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return (ENOSPC);
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law_write(i, bar, sr);
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return (0);
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}
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int
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law_disable(int trgt, uint64_t bar, uint32_t size)
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{
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uint64_t bar_tmp;
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uint32_t sr, sr_tmp;
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int i, law_max;
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law_max = law_getmax();
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sr = _LAW_SR(trgt, size);
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/* Find and disable requested LAW. */
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for (i = 0; i < law_max; i++) {
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law_read(i, &bar_tmp, &sr_tmp);
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if (sr == sr_tmp && bar == bar_tmp) {
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law_write(i, 0, 0);
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return (0);
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}
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}
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return (ENOENT);
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}
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int
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law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io)
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{
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u_long start;
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uint32_t ver;
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int trgt, rv;
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ver = SVR_VER(mfspr(SPR_SVR));
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start = rman_get_start(res) & 0xf000;
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rv = 0;
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trgt = -1;
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switch (start) {
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case 0x0000:
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case 0x8000:
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trgt = 0;
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break;
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case 0x1000:
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case 0x9000:
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trgt = 1;
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break;
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case 0x2000:
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case 0xa000:
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if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
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trgt = 3;
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else
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trgt = 2;
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break;
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case 0x3000:
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case 0xb000:
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if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
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rv = EINVAL;
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else
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trgt = 3;
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break;
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default:
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rv = ENXIO;
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}
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if (rv == 0) {
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*trgt_mem = trgt;
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*trgt_io = trgt;
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}
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return (rv);
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}
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static void
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l3cache_inval(void)
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{
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/* Flash invalidate the CPC and clear all the locks */
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ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI |
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OCP85XX_CPC_CSR0_LFC);
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while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI |
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OCP85XX_CPC_CSR0_LFC))
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;
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}
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static void
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l3cache_enable(void)
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{
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ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE |
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OCP85XX_CPC_CSR0_PE);
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/* Read back to sync write */
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ccsr_read4(OCP85XX_CPC_CSR0);
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}
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void
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mpc85xx_enable_l3_cache(void)
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{
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uint32_t csr, size, ver;
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/* Enable L3 CoreNet Platform Cache (CPC) */
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ver = SVR_VER(mfspr(SPR_SVR));
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if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 ||
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ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) {
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csr = ccsr_read4(OCP85XX_CPC_CSR0);
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if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
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l3cache_inval();
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l3cache_enable();
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}
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csr = ccsr_read4(OCP85XX_CPC_CSR0);
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if ((boothowto & RB_VERBOSE) != 0 ||
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(csr & OCP85XX_CPC_CSR0_CE) == 0) {
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size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0));
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printf("L3 Corenet Platform Cache: %d KB %sabled\n",
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size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
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"dis" : "en");
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}
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}
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}
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int
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mpc85xx_is_qoriq(void)
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{
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uint16_t pvr = mfpvr() >> 16;
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/* QorIQ register set is only in e500mc and derivative core based SoCs. */
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if (pvr == FSL_E500mc || pvr == FSL_E5500 || pvr == FSL_E6500)
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return (1);
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return (0);
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}
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static void
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mpc85xx_dataloss_erratum_spr976(void)
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{
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uint32_t svr = SVR_VER(mfspr(SPR_SVR));
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/* Ignore whether it's the E variant */
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svr &= ~0x8;
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if (svr != SVR_P3041 && svr != SVR_P4040 &&
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svr != SVR_P4080 && svr != SVR_P5020)
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return;
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mb();
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isync();
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mtspr(976, (mfspr(976) & ~0x1f8) | 0x48);
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isync();
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}
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static vm_offset_t
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mpc85xx_map_dcsr(void)
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{
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phandle_t node;
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u_long b, s;
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int err;
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/*
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* Try to access the dcsr node directly i.e. through /aliases/.
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*/
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if ((node = OF_finddevice("dcsr")) != -1)
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if (fdt_is_compatible_strict(node, "fsl,dcsr"))
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goto moveon;
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/*
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* Find the node the long way.
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*/
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if ((node = OF_finddevice("/")) == -1)
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return (0);
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if ((node = ofw_bus_find_compatible(node, "fsl,dcsr")) == 0)
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return (0);
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moveon:
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err = fdt_get_range(node, 0, &b, &s);
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if (err != 0)
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return (0);
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law_enable(OCP85XX_TGTIF_DCSR, b, 0x400000);
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return pmap_early_io_map(b, 0x400000);
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}
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void
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mpc85xx_fix_errata(vm_offset_t va_ccsr)
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{
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uint32_t svr = SVR_VER(mfspr(SPR_SVR));
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vm_offset_t va_dcsr;
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/* Ignore whether it's the E variant */
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svr &= ~0x8;
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if (svr != SVR_P3041 && svr != SVR_P4040 &&
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svr != SVR_P4080 && svr != SVR_P5020)
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return;
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if (mfmsr() & PSL_EE)
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return;
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/*
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* dcsr region need to be mapped thus patch can refer to.
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* Align dcsr right after ccsbar.
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*/
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va_dcsr = mpc85xx_map_dcsr();
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if (va_dcsr == 0)
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goto err;
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/*
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* As A004510 errata specify, special purpose register 976
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* SPR976[56:60] = 6'b001001 must be set. e500mc core reference manual
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* does not document SPR976 register.
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*/
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mpc85xx_dataloss_erratum_spr976();
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/*
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* Specific settings in the CCF and core platform cache (CPC)
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* are required to reconfigure the CoreNet coherency fabric.
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* The register settings that should be updated are described
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* in errata and relay on base address, offset and updated value.
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* Special conditions must be used to update these registers correctly.
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*/
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dataloss_erratum_access(va_dcsr + 0xb0e08, 0xe0201800);
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dataloss_erratum_access(va_dcsr + 0xb0e18, 0xe0201800);
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dataloss_erratum_access(va_dcsr + 0xb0e38, 0xe0400000);
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dataloss_erratum_access(va_dcsr + 0xb0008, 0x00900000);
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dataloss_erratum_access(va_dcsr + 0xb0e40, 0xe00a0000);
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switch (svr) {
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case SVR_P5020:
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dataloss_erratum_access(va_ccsr + 0x18600, 0xc0000000);
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break;
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case SVR_P4040:
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case SVR_P4080:
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dataloss_erratum_access(va_ccsr + 0x18600, 0xff000000);
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break;
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case SVR_P3041:
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dataloss_erratum_access(va_ccsr + 0x18600, 0xf0000000);
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}
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dataloss_erratum_access(va_ccsr + 0x10f00, 0x415e5000);
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dataloss_erratum_access(va_ccsr + 0x11f00, 0x415e5000);
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err:
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return;
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}
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uint32_t
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mpc85xx_get_platform_clock(void)
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{
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phandle_t soc;
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static uint32_t freq;
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if (freq != 0)
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return (freq);
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soc = OF_finddevice("/soc");
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/* freq isn't modified on error. */
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OF_getencprop(soc, "bus-frequency", (void *)&freq, sizeof(freq));
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return (freq);
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}
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uint32_t
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mpc85xx_get_system_clock(void)
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{
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uint32_t freq;
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freq = mpc85xx_get_platform_clock();
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return (freq / 2);
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}
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