Adrian Chadd aefdcce869 [mips] print out l2 cache configuration if it exists. ... The Ingenic JZ7480 SoC that is on the Imagination Technologies CI20 board has an L2 cache: Cache info: picache_stride = 4096 picache_loopcount = 8 pdcache_stride = 4096 pdcache_loopcount = 8 cpu0: Ingenic Xburst processor v79.2 MMU: Standard TLB, 32 entries L1 i-cache: 8 ways of 128 sets, 32 bytes per line L1 d-cache: 8 ways of 128 sets, 32 bytes per line L2 cache: 8 ways of 256 sets, 128 bytes per line, 256 KiB total size Config1=0xbe67338b<WatchRegs,EJTAG,FPU> Config2=0x80000267 Config3=0x20		2015-12-21 01:48:16 +00:00
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adm5120	Add domain support to PCI bus allocation	2015-09-16 23:34:51 +00:00
alchemy	Fix a typo introduced in r257338.	2013-10-31 02:27:16 +00:00
atheros	[qca953x] remove unneeded initialisation.	2015-12-15 04:45:00 +00:00
beri	preload_search_info: make sure mod is set	2015-08-21 15:57:57 +00:00
cavium	Add domain support to PCI bus allocation	2015-09-16 23:34:51 +00:00
conf	Add support for the integrated wifi for the QCA953x base config and	2015-11-29 05:49:49 +00:00
gxemul	Add 32-bit support for Gxemul's oldtestmips machine emulation	2013-09-04 20:34:36 +00:00
idt	Add domain support to PCI bus allocation	2015-09-16 23:34:51 +00:00
include	Tidy up mips ofw_machdep.h. Don't include openfirm.h because openfirm.h	2015-12-20 19:09:12 +00:00
malta	[mips]: Don't hard-code PHYS_AVAIL_ENTRIES.	2015-11-22 02:40:19 +00:00
mips	[mips] print out l2 cache configuration if it exists.	2015-12-21 01:48:16 +00:00
nlm	Add domain support to PCI bus allocation	2015-09-16 23:34:51 +00:00
rmi	Add domain support to PCI bus allocation	2015-09-16 23:34:51 +00:00
rt305x	Add support for the uart classes to set their default register shift value.	2015-04-11 17:16:23 +00:00
sentry5	Merge from vmobj-rwlock branch:	2013-02-26 01:00:11 +00:00
sibyte	Devices that rely on hints or identify routines for discovery need to	2013-10-29 14:07:31 +00:00