4f2702c1c3
Communication on src-commiters, Sat, 27 Apr 2013 22:09:06 -0700, Subject was: "Re: svn commit: r249997" As I'm here, fix the style main block comments in files' headers.
303 lines
7.8 KiB
C
303 lines
7.8 KiB
C
/*-
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* Copyright (c) 2013 Thomas Skibo
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.
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* In the future, maybe MIO control, clock control, etc. could go here.
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*
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* Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
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* (v1.4) November 16, 2012. Xilinx doc UG585.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/sysctl.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/stdarg.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/xilinx/zy7_slcr.h>
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struct zy7_slcr_softc {
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device_t dev;
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struct mtx sc_mtx;
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struct resource *mem_res;
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};
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static struct zy7_slcr_softc *zy7_slcr_softc_p;
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extern void (*zynq7_cpu_reset);
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#define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
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#define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
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#define ZSLCR_LOCK_INIT(sc) \
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mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
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"zy7_slcr", MTX_SPIN)
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#define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
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#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
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SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000");
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static char zynq_bootmode[64];
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SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0,
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"Zynq boot mode");
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static char zynq_pssid[80];
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SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0,
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"Zynq PSS IDCODE");
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static uint32_t zynq_reboot_status;
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SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status,
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0, "Zynq REBOOT_STATUS register");
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static void
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zy7_slcr_unlock(struct zy7_slcr_softc *sc)
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{
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/* Unlock SLCR with magic number. */
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WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC);
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}
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static void
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zy7_slcr_lock(struct zy7_slcr_softc *sc)
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{
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/* Lock SLCR with magic number. */
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WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC);
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}
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static void
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zy7_slcr_cpu_reset(void)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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/* This has something to do with a work-around so the fsbl will load
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* the bitstream after soft-reboot. It's very important.
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*/
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WR4(sc, ZY7_SLCR_REBOOT_STAT,
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RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff);
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/* Soft reset */
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WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET);
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for (;;)
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;
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}
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/* Assert PL resets and disable level shifters in preparation of programming
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* the PL (FPGA) section. Called from zy7_devcfg.c.
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*/
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void
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zy7_slcr_preload_pl(void)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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if (!sc)
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return;
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ZSLCR_LOCK(sc);
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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/* Assert top level output resets. */
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WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL);
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/* Disable all level shifters. */
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WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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ZSLCR_UNLOCK(sc);
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}
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/* After PL configuration, enable level shifters and deassert top-level
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* PL resets. Called from zy7_devcfg.c. Optionally, the level shifters
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* can be left disabled but that's rare of an FPGA application. That option
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* is controled by a sysctl in the devcfg driver.
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*/
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void
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zy7_slcr_postload_pl(int en_level_shifters)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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if (!sc)
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return;
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ZSLCR_LOCK(sc);
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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if (en_level_shifters)
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/* Enable level shifters. */
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WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
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/* Deassert top level output resets. */
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WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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ZSLCR_UNLOCK(sc);
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}
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static int
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zy7_slcr_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "xlnx,zy7_slcr"))
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return (ENXIO);
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device_set_desc(dev, "Zynq-7000 slcr block");
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return (0);
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}
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static int
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zy7_slcr_attach(device_t dev)
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{
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struct zy7_slcr_softc *sc = device_get_softc(dev);
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int rid;
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uint32_t bootmode;
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uint32_t pss_idcode;
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static char *bootdev_names[] = {
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"JTAG", "Quad-SPI", "NOR", "(3?)",
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"NAND", "SD Card", "(6?)", "(7?)"
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};
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/* Allow only one attach. */
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if (zy7_slcr_softc_p != NULL)
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return (ENXIO);
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sc->dev = dev;
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ZSLCR_LOCK_INIT(sc);
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/* Get memory resource. */
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "could not allocate memory resources.\n");
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return (ENOMEM);
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}
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/* Hook up cpu_reset. */
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zy7_slcr_softc_p = sc;
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zynq7_cpu_reset = zy7_slcr_cpu_reset;
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/* Read info and set sysctls. */
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bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE);
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snprintf(zynq_bootmode, sizeof(zynq_bootmode),
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"0x%x: boot device: %s", bootmode,
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bootdev_names[bootmode & ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK]);
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pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE);
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snprintf(zynq_pssid, sizeof(zynq_pssid),
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"0x%x: manufacturer: 0x%x device: 0x%x "
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"family: 0x%x sub-family: 0x%x rev: 0x%x",
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pss_idcode,
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(pss_idcode & ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK) >>
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ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT,
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(pss_idcode & ZY7_SLCR_PSS_IDCODE_DEVICE_MASK) >>
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ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT,
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(pss_idcode & ZY7_SLCR_PSS_IDCODE_FAMILY_MASK) >>
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ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT,
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(pss_idcode & ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK) >>
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ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT,
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(pss_idcode & ZY7_SLCR_PSS_IDCODE_REVISION_MASK) >>
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ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT);
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zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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return (0);
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}
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static int
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zy7_slcr_detach(device_t dev)
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{
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struct zy7_slcr_softc *sc = device_get_softc(dev);
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bus_generic_detach(dev);
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/* Release memory resource. */
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if (sc->mem_res != NULL)
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bus_release_resource(dev, SYS_RES_MEMORY,
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rman_get_rid(sc->mem_res), sc->mem_res);
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zy7_slcr_softc_p = NULL;
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zynq7_cpu_reset = NULL;
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ZSLCR_LOCK_DESTROY(sc);
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return (0);
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}
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static device_method_t zy7_slcr_methods[] = {
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/* device_if */
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DEVMETHOD(device_probe, zy7_slcr_probe),
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DEVMETHOD(device_attach, zy7_slcr_attach),
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DEVMETHOD(device_detach, zy7_slcr_detach),
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DEVMETHOD_END
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};
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static driver_t zy7_slcr_driver = {
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"zy7_slcr",
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zy7_slcr_methods,
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sizeof(struct zy7_slcr_softc),
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};
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static devclass_t zy7_slcr_devclass;
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DRIVER_MODULE(zy7_slcr, simplebus, zy7_slcr_driver, zy7_slcr_devclass, 0, 0);
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MODULE_VERSION(zy7_slcr, 1);
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