6fb6b7ee36
o define HAL_SOFTC, HAL_BUS_TAG, and HAL_BUS_HANDLE to be machine independent; this fixes portability issues with bsd systems o add ah_disable api for turning off operation of both MAC and PHY o add ah_getAntennaSwitch and ah_setAntennaSwitch api's for better control of antenna usage and diversity o add ah_setAckCTSRate and ah_setAckCTSRate for controlling tx rate of h/w generated frames o add ah_setBeaconTimers api for simpler setting of the beacon timer registers o remove ah_waitForBeaconDone api o add HAL_TXDESC_DURENA flag to enable h/w duration setting in tx descriptor o correct documentation of min/max tx power units (.5 dBm) o switch arm, mips, and powerpc builds to use functions for register read/write operations o fix sparc builds to not reference %g2 and %g3 registers o add public builds for SoC's MFC after: 1 month
111 lines
4.9 KiB
C
111 lines
4.9 KiB
C
/*-
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* Copyright (c) 2006 Sam Leffler, Errno Consulting, Atheros
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* Communications, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms are permitted
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* provided that the following conditions are met:
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* 1. The materials contained herein are unmodified and are used
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* unmodified.
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* 2. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following NO
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* ''WARRANTY'' disclaimer below (''Disclaimer''), without
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* modification.
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* 3. Redistributions in binary form must reproduce at minimum a
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* disclaimer similar to the Disclaimer below and any redistribution
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* must be conditioned upon including a substantially similar
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* Disclaimer requirement for further binary redistribution.
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* 4. Neither the names of the above-listed copyright holders nor the
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* names of any contributors may be used to endorse or promote
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* product derived from this software without specific prior written
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* permission.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
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* MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
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* FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGES.
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*
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* $Id: //depot/sw/branches/sam_hal/ah_soc.h#3 $
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*/
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#ifndef _ATH_AH_SOC_H_
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#define _ATH_AH_SOC_H_
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/*
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* Atheros System on Chip (SoC) public definitions.
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*/
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/*
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* This is board-specific data that is stored in a "known"
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* location in flash. To find the start of this data search
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* back from the (aliased) end of flash by 0x1000 bytes at a
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* time until you find the string "5311", which marks the
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* start of Board Configuration. Typically one gives up if
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* more than 500KB is searched.
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*/
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struct ar531x_boarddata {
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u_int32_t magic; /* board data is valid */
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#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
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u_int16_t cksum; /* checksum (starting with BD_REV 2) */
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u_int16_t rev; /* revision of this struct */
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#define BD_REV 4
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char boardName[64]; /* Name of board */
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u_int16_t major; /* Board major number */
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u_int16_t minor; /* Board minor number */
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u_int32_t config; /* Board configuration */
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#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
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#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
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#define BD_UART1 0x00000004 /* UART1 is stuffed */
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#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
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#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
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#define BD_SYSLED 0x00000020 /* System LED stuffed */
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#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
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#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
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#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
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#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
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#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */
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#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
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#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
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#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
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#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
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#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
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#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
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#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
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u_int16_t resetConfigGpio; /* Reset factory GPIO pin */
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u_int16_t sysLedGpio; /* System LED GPIO pin */
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u_int32_t cpuFreq; /* CPU core frequency in Hz */
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u_int32_t sysFreq; /* System frequency in Hz */
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u_int32_t cntFreq; /* Calculated C0_COUNT frequency */
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u_int8_t wlan0Mac[6];
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u_int8_t enet0Mac[6];
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u_int8_t enet1Mac[6];
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u_int16_t pciId; /* Pseudo PCIID for common code */
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u_int16_t memCap; /* cap bank1 in MB */
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/* version 3 */
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u_int8_t wlan1Mac[6]; /* (ar5212) */
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};
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/*
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* Board support data. The driver is required to locate
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* and fill-in this information before passing a reference to
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* this structure as the HAL_BUS_TAG parameter supplied to
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* ath_hal_attach.
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*/
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struct ar531x_config {
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const struct ar531x_boarddata *board; /* board config data */
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const char *radio; /* radio config data */
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int unit; /* unit number [0, 1] */
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void *tag; /* bus space tag */
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};
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#endif /* _ATH_AH_SOC_H_ */
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