mmel a0d10caff7 EHCI: Make core reset and port speed reading more generic. ... Use driver settable callbacks for handling of: - core post reset - reading actual port speed Typically, OTG enabled EHCI cores wants setting of USBMODE register, but this register is not defined in EHCI specification and different cores can have it on different offset. Also, for cores with TT extension, actual port speed must be determinable. But again, EHCI specification not covers this so this patch provides function for two most common variant of speed bits layout. Reviewed by: hselasky Differential Revision: https://reviews.freebsd.org/D5088		2016-01-28 14:11:59 +00:00
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zedboard
files.zynq7	Create device options for the two common ARM timers.	2015-11-21 16:23:56 +00:00
std.zynq7	Stop setting {KERN,}PHYSADDR on armv6, it's unneeded.	2015-11-20 16:12:22 +00:00
uart_dev_cdnc.c	Move the uart_class definitions and fdt compat data into the individual	2015-03-07 15:24:15 +00:00
zy7_devcfg.c	Add sysctls to control PS-PL level shifters and FCLK settings.	2015-03-05 21:41:58 +00:00
zy7_ehci.c	EHCI: Make core reset and port speed reading more generic.	2016-01-28 14:11:59 +00:00
zy7_gpio.c	Implement GPIO_GET_BUS() method for all GPIO drivers.	2015-01-31 19:32:14 +00:00
zy7_l2cache.c
zy7_machdep.c	opt_global.h is included automatically in the build. No need to	2014-11-18 17:06:56 +00:00
zy7_mp.c	[intrng] Migrate the intrng code from sys/arm/arm to sys/kern/subr_intr.c.	2015-12-18 05:43:59 +00:00
zy7_reg.h	Convert the Zynq SoC support to the new routines for static device mapping.	2014-04-30 14:38:13 +00:00
zy7_slcr.c	Add sysctls to control PS-PL level shifters and FCLK settings.	2015-03-05 21:41:58 +00:00
zy7_slcr.h	Add sysctls to control PS-PL level shifters and FCLK settings.	2015-03-05 21:41:58 +00:00