19d3b47b92
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
209 lines
7.4 KiB
C
209 lines
7.4 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* NETLOGIC_BSD
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* $FreeBSD$
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*/
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#ifndef __NLM_HAL_IOMAP_H__
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#define __NLM_HAL_IOMAP_H__
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#define XLP_DEFAULT_IO_BASE 0x18000000
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#define NMI_BASE 0xbfc00000
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#define XLP_IO_CLK 133333333
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#define XLP_L2L3_CACHELINE_SIZE 64
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#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */
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#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE)
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#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE)
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#define XLP_IO_SIZE (64 << 20) /* ECFG space size */
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#define XLP_IO_PCI_HDRSZ 0x100
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#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8)
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#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \
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((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))
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#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0)
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/* coherent inter chip */
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#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1)
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#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2)
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#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3)
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#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4)
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#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i)
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#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0)
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#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1)
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#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2)
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#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3)
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#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i)
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#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0)
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#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1)
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#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2)
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#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3)
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#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
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#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
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#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
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#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
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#define XLP_IO_SATA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 2)
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#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0)
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#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 0)
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#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1)
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#define XLP_IO_RSA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2)
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#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3)
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#define XLP_IO_SRIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 4)
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#define XLP_IO_REGEX_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 5)
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#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i)
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#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0)
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#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1)
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#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i)
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#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
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#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
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#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
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/* system management */
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#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
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#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
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#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0)
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#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1)
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#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2)
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/* SD flash */
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#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
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#define XLP_IO_MMC_OFFSET(node, slot) \
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((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
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/* PCI config header register id's */
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#define XLP_PCI_CFGREG0 0x00
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#define XLP_PCI_CFGREG1 0x01
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#define XLP_PCI_CFGREG2 0x02
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#define XLP_PCI_CFGREG3 0x03
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#define XLP_PCI_CFGREG4 0x04
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#define XLP_PCI_CFGREG5 0x05
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#define XLP_PCI_DEVINFO_REG0 0x30
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#define XLP_PCI_DEVINFO_REG1 0x31
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#define XLP_PCI_DEVINFO_REG2 0x32
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#define XLP_PCI_DEVINFO_REG3 0x33
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#define XLP_PCI_DEVINFO_REG4 0x34
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#define XLP_PCI_DEVINFO_REG5 0x35
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#define XLP_PCI_DEVINFO_REG6 0x36
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#define XLP_PCI_DEVINFO_REG7 0x37
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#define XLP_PCI_DEVSCRATCH_REG0 0x38
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#define XLP_PCI_DEVSCRATCH_REG1 0x39
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#define XLP_PCI_DEVSCRATCH_REG2 0x3a
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#define XLP_PCI_DEVSCRATCH_REG3 0x3b
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#define XLP_PCI_MSGSTN_REG 0x3c
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#define XLP_PCI_IRTINFO_REG 0x3d
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#define XLP_PCI_UCODEINFO_REG 0x3e
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#define XLP_PCI_SBB_WT_REG 0x3f
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/* PCI IDs for SoC device */
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#define PCI_VENDOR_NETLOGIC 0x184e
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#define PCI_DEVICE_ID_NLM_ROOT 0x1001
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#define PCI_DEVICE_ID_NLM_ICI 0x1002
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#define PCI_DEVICE_ID_NLM_PIC 0x1003
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#define PCI_DEVICE_ID_NLM_PCIE 0x1004
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#define PCI_DEVICE_ID_NLM_EHCI 0x1007
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#define PCI_DEVICE_ID_NLM_ILK 0x1008
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#define PCI_DEVICE_ID_NLM_NAE 0x1009
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#define PCI_DEVICE_ID_NLM_POE 0x100A
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#define PCI_DEVICE_ID_NLM_FMN 0x100B
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#define PCI_DEVICE_ID_NLM_RAID 0x100D
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#define PCI_DEVICE_ID_NLM_SAE 0x100D
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#define PCI_DEVICE_ID_NLM_RSA 0x100E
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#define PCI_DEVICE_ID_NLM_CMP 0x100F
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#define PCI_DEVICE_ID_NLM_UART 0x1010
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#define PCI_DEVICE_ID_NLM_I2C 0x1011
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#define PCI_DEVICE_ID_NLM_NOR 0x1015
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#define PCI_DEVICE_ID_NLM_NAND 0x1016
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#define PCI_DEVICE_ID_NLM_MMC 0x1018
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r)
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#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v)
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extern uint64_t xlp_sys_base;
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extern uint64_t xlp_pic_base;
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static __inline__ int
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nlm_dev_exists(uint32_t devoffset)
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{
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uint64_t pcibase = nlm_pcicfg_base(devoffset);
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return (nlm_read_reg(pcibase, XLP_PCI_CFGREG0) != 0xffffffff);
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}
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static __inline__ int
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nlm_qidstart(uint64_t pcibase)
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{
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return (nlm_read_reg(pcibase, XLP_PCI_MSGSTN_REG) & 0xffff);
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}
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static __inline__ int
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nlm_qnum(uint64_t pcibase)
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{
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return (nlm_read_reg(pcibase, XLP_PCI_MSGSTN_REG) >> 16);
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}
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static __inline__ int
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nlm_irtstart(uint64_t pcibase)
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{
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return (nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff);
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}
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static __inline__ int
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nlm_irtnum(uint64_t pcibase)
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{
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return (nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) >> 16);
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}
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static __inline__ int
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nlm_num_uengines(uint64_t pcibase)
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{
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return nlm_read_reg(pcibase, XLP_PCI_UCODEINFO_REG);
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}
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/*
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* Find node on which a given Soc device is located.
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* input is the pci device (slot) number.
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*/
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static __inline__ int
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nlm_get_device_node(int device)
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{
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return (device / 8);
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}
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#endif /* !LOCORE or !__ASSEMBLY */
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#endif /* __NLM_HAL_IOMAP_H__ */
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