136 lines
4.9 KiB
C
136 lines
4.9 KiB
C
/*-
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* Exported interface to downloadable microcode for AdvanSys SCSI Adapters
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*
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* $FreeBSD$
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*
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* Obtained from:
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*
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* Copyright (c) 1995-1999 Advanced System Products, Inc.
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* All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that redistributions of source
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* code retain the above copyright notice and this comment without
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* modification.
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*/
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#ifndef _ADMCODE_H_
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#define _ADMCODE_H_
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struct adw_mcode
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{
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const u_int8_t* mcode_buf;
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const u_int32_t mcode_chksum;
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const u_int16_t mcode_size;
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};
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extern const struct adw_mcode adw_asc3550_mcode_data;
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extern const struct adw_mcode adw_asc38C0800_mcode_data;
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/*
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* Fixed LRAM locations of microcode operating variables.
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*/
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#define ADW_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
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#define ADW_MC_CODE_END_ADDR 0x002A /* microcode end address */
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#define ADW_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
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#define ADW_MC_VERSION_DATE 0x0038 /* microcode version */
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#define ADW_MC_VERSION_NUM 0x003A /* microcode number */
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#define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
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#define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
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#define ADW_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
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#define ADW_MC_BIOS_VERSION 0x005A /* BIOS Version (2 Bytes) */
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#define ADW_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
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#define ADW_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
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#define ADW_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
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#define ADW_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
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#define ADW_MC_CHIP_TYPE 0x009A
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#define ADW_MC_INTRB_CODE 0x009B
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#define ADW_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
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#define ADW_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected Bus Reset. */
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#define ADW_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure.*/
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#define ADW_ASYNC_HOST_SCSI_BUS_RESET 0x80 /*
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* Host Initiated
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* SCSI Bus Reset.
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*/
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#define ADW_MC_WDTR_ABLE_BIOS_31 0x0120
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#define ADW_MC_WDTR_ABLE 0x009C
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#define ADW_MC_SDTR_ABLE 0x009E
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#define ADW_MC_TAGQNG_ABLE 0x00A0
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#define ADW_MC_DISC_ENABLE 0x00A2
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#define ADW_MC_IDLE_CMD_STATUS 0x00A4
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#define ADW_MC_IDLE_CMD 0x00A6
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#define ADW_MC_IDLE_CMD_PARAMETER 0x00A8
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#define ADW_MC_DEFAULT_SCSI_CFG0 0x00AC
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#define ADW_MC_DEFAULT_SCSI_CFG1 0x00AE
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#define ADW_MC_DEFAULT_MEM_CFG 0x00B0
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#define ADW_MC_DEFAULT_SEL_MASK 0x00B2
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#define ADW_MC_RISC_NEXT_READY 0x00B4
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#define ADW_MC_RISC_NEXT_DONE 0x00B5
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#define ADW_MC_SDTR_DONE 0x00B6
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#define ADW_MC_NUMBER_OF_QUEUED_CMD 0x00C0
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#define ADW_MC_NUMBER_OF_MAX_CMD 0x00D0
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#define ADW_MC_DEVICE_HSHK_CFG_TABLE 0x0100
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#define ADW_HSHK_CFG_WIDE_XFR 0x8000
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#define ADW_HSHK_CFG_RATE_MASK 0x7F00
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#define ADW_HSHK_CFG_RATE_SHIFT 8
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#define ADW_HSHK_CFG_OFFSET 0x001F
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#define ADW_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
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#define ADW_MC_CONTROL_IGN_PERR 0x0001 /* Ignore DMA Parity Errors */
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#define ADW_MC_WDTR_DONE 0x0124
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#define ADW_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
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#define ADW_MC_ICQ 0x0160
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#define ADW_MC_IRQ 0x0164
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/* ADW_SCSI_REQ_Q 'cntl' field values */
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#define ADW_QC_DATA_CHECK 0x01 /* Require ADW_QC_DATA_OUT set or clear. */
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#define ADW_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
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#define ADW_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
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#define ADW_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
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#define ADW_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request.XXXTBD */
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#define ADW_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
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#define ADW_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
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#define ADW_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request.*/
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#define ADW_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
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#define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request.*/
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/*
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* Note: If a Tag Message is to be sent and neither ADW_QSC_HEAD_TAG or
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* ADW_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
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*/
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#define ADW_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
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#define ADW_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
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struct adw_carrier
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{
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u_int32_t carr_offset; /* Carrier byte offset into our array */
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u_int32_t carr_ba; /* Carrier Bus Address */
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u_int32_t areq_ba; /* SCSI Req Queue Bus Address */
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u_int32_t next_ba;
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#define ADW_RQ_DONE 0x00000001
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#define ADW_CQ_STOPPER 0x00000000
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#define ADW_NEXT_BA_MASK 0xFFFFFFF0
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};
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/*
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* Microcode idle loop commands
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*/
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typedef enum {
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ADW_IDLE_CMD_COMPLETED = 0x0000,
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ADW_IDLE_CMD_STOP_CHIP = 0x0001,
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ADW_IDLE_CMD_STOP_CHIP_SEND_INT = 0x0002,
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ADW_IDLE_CMD_SEND_INT = 0x0004,
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ADW_IDLE_CMD_ABORT = 0x0008,
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ADW_IDLE_CMD_DEVICE_RESET = 0x0010,
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ADW_IDLE_CMD_SCSI_RESET_START = 0x0020,
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ADW_IDLE_CMD_SCSI_RESET_END = 0x0040,
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ADW_IDLE_CMD_SCSIREQ = 0x0080
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} adw_idle_cmd_t;
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typedef enum {
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ADW_IDLE_CMD_FAILURE = 0x0000,
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ADW_IDLE_CMD_SUCCESS = 0x0001
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} adw_idle_cmd_status_t;
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#endif /* _ADMCODE_H_ */
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