8088699f79
type of software interrupt. Roughly, what used to be a bit in spending now maps to a swi thread. Each thread can have multiple handlers, just like a hardware interrupt thread. - Instead of using a bitmask of pending interrupts, we schedule the specific software interrupt thread to run, so spending, NSWI, and the shandlers array are no longer needed. We can now have an arbitrary number of software interrupt threads. When you register a software interrupt thread via sinthand_add(), you get back a struct intrhand that you pass to sched_swi() when you wish to schedule your swi thread to run. - Convert the name of 'struct intrec' to 'struct intrhand' as it is a bit more intuitive. Also, prefix all the members of struct intrhand with 'ih_'. - Make swi_net() a MI function since there is now no point in it being MD. Submitted by: cp
187 lines
5.3 KiB
ArmAsm
187 lines
5.3 KiB
ArmAsm
/*-
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* Copyright (c) 1989, 1990 William F. Jolitz.
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)ipl.s
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*
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* $FreeBSD$
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*/
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/*
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* AT/386
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* Vector interrupt control section
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*
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* *_imask - Interrupt masks for various spl*() functions
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* ipending - Pending interrupts (set when a masked interrupt occurs)
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*/
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.data
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ALIGN_DATA
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/* current priority (all off) */
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.globl _tty_imask
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_tty_imask: .long 0
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.globl _bio_imask
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_bio_imask: .long 0
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.globl _net_imask
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_net_imask: .long 0
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.globl _cam_imask
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_cam_imask: .long 0
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.globl _soft_imask
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_soft_imask: .long 0
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.globl _softnet_imask
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_softnet_imask: .long 0
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.globl _softtty_imask
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_softtty_imask: .long 0
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/* pending software interrupts */
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.globl _spending
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_spending: .long 0
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/* set with bits for which queue to service */
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.globl _netisr
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_netisr: .long 0
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.globl _netisrs
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_netisrs:
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.text
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/*
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* Handle return from interrupts, traps and syscalls.
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*/
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SUPERALIGN_TEXT
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.type _doreti,@function
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_doreti:
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FAKE_MCOUNT(_bintr) /* init "from" _bintr -> _doreti */
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addl $4,%esp /* discard unit number */
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doreti_next:
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decb _intr_nesting_level
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/* Check for ASTs that can be handled now. */
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testl $AST_PENDING,_astpending
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je doreti_exit /* no AST, exit */
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testb $SEL_RPL_MASK,TF_CS(%esp) /* are we in user mode? */
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jne doreti_ast /* yes, do it now. */
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testl $PSL_VM,TF_EFLAGS(%esp) /* kernel mode */
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je doreti_exit /* and not VM86 mode, defer */
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cmpl $1,_in_vm86call /* are we in a VM86 call? */
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jne doreti_ast /* yes, we can do it */
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/*
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* doreti_exit: release MP lock, pop registers, iret.
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*
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* Note that the syscall trap shortcuts to doreti_syscall_ret.
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* The segment register pop is a special case, since it may
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* fault if (for example) a sigreturn specifies bad segment
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* registers. The fault is handled in trap.c.
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*/
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doreti_exit:
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MEXITCOUNT
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.globl doreti_popl_fs
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.globl doreti_syscall_ret
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doreti_syscall_ret:
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doreti_popl_fs:
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popl %fs
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.globl doreti_popl_es
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doreti_popl_es:
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popl %es
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.globl doreti_popl_ds
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doreti_popl_ds:
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popl %ds
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popal
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addl $8,%esp
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.globl doreti_iret
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doreti_iret:
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iret
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/*
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* doreti_iret_fault and friends. Alternative return code for
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* the case where we get a fault in the doreti_exit code
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* above. trap() (i386/i386/trap.c) catches this specific
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* case, sends the process a signal and continues in the
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* corresponding place in the code below.
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*/
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ALIGN_TEXT
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.globl doreti_iret_fault
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doreti_iret_fault:
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subl $8,%esp
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pushal
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pushl %ds
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.globl doreti_popl_ds_fault
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doreti_popl_ds_fault:
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pushl %es
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.globl doreti_popl_es_fault
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doreti_popl_es_fault:
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pushl %fs
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.globl doreti_popl_fs_fault
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doreti_popl_fs_fault:
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movl $0,TF_ERR(%esp) /* XXX should be the error code */
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movl $T_PROTFLT,TF_TRAPNO(%esp)
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jmp alltraps_with_regs_pushed
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ALIGN_TEXT
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doreti_ast:
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andl $~AST_PENDING,_astpending
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sti
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movl $T_ASTFLT,TF_TRAPNO(%esp)
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call _ast
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movb $1,_intr_nesting_level /* for doreti_next to decrement */
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jmp doreti_next
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ALIGN_TEXT
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dummynetisr:
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MCOUNT
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ret
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#ifdef APIC_IO
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#include "i386/isa/apic_ipl.s"
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#else
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#include "i386/isa/icu_ipl.s"
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#endif /* APIC_IO */
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